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| ? 2015 microchip technology inc. ds20005466a-page 1 mcp48fvbxx features operating voltage range: - 2.7v to 5.5v - full specifications - 1.8v to 2.7v - reduced device specifications output voltage resolutions: - 8-bit: mcp48fvb0x (256 steps) - 10-bit: mcp48fvb1x (1024 steps) - 12-bit: mcp48fvb2x (4096 steps) rail-to-rail output fast settling time of 7.8 s (typical) dac voltage reference source options: - device v dd -external v ref pin (buffered or unbuffered) - internal band gap (1.22v typical) output gain options: - unity (1x) -2x power-on/brown-out reset protection power-down modes: - disconnects output buffer (high impedance) - selection of v out pull-down resistors (100 k ? or 1 k ? ) low power consumption: - normal operation: <180 a (single), 380 a (dual) - power-down operation: 650 na typical spi interface: - supports 00 and 11 modes - up to 20 mhz writes and 10 mhz reads - input buffers support interfacing to low-voltage digital devices package types: 10-lead msop extended temperature range: -40c to +125c package types general description the mcp48fvbxx are single- and dual-channel 8-bit, 10-bit, and 12-bit buffered voltage output digital-to-analog converters (dac) with volatile memory and an spi serial interface. the v ref pin, the device v dd or the internal band gap voltage can be selected as the dacs reference voltage. when v dd is selected, v dd is connected internally to the dac reference circuit. when the v ref pin is used, the user can select the output buffers gain to be 1 or 2. when the gain is 2, the v ref pin voltage should be limited to a maximum of v dd /2. these devices have an spi-compatible serial interface. write commands are supported up to 20 mhz while read commands are supported up to 10 mhz. applications set point or offset trimming sensor calibration low-power portable instrumentation pc peripherals data acquisition systems motor control dual single mcp48fvbx2 msop mcp48fvbx1 12 3 4 7 8 9 10 v ss v out0 v ref0 cs v dd sck sdi sdo 5 6 lat0 /hvc nc msop 12 3 4 7 8 9 10 v ss v out0 cs v dd sck sdi sdo 56 v out1 note 1: associated with both dac0 and dac1 v ref ( 1 ) lat /hvc ( 1 ) 8-/10-/12-bit single/dual voltage output volatile digital-to-analog converters with spi interface downloaded from: http:///
mcp48fvbxx ds20005466a-page 2 ? 2015 microchip technology inc. mcp48fvbx1 device block diagram (single-channel output) power-up/ brown-out control v dd v ss spi serial interface module memory (32x16) dac0 (vol) v ref0 op amp gain v out0 lat0 /hvc resistor ladder v ss pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd sdi sdo band gap (1.22v) pd1:pd0 vref1:vref0 v dd v bg pd1:pd0 1k ? 100 k ? vref (vol) power-down (vol) gain (vol) status (vol) and pd1:pd0 note 1: if internal band gap is selected, this buffer has a 2x gain. if the g bit = 1 , this is a total gain of 4. sck cs and control logic ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 3 mcp48fvbxx mcp48fvbx2 device block diagram (dual-channel output) power-up/ brown-out control v dd v ss spi serial interface module v ref lat /hvc resistor ladder op amp gain v out1 resistor ladder intvr1 pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd sdi sdo band gap (1.22v) band gap (1.22v) pd1:pd0 v dd v bg v dd v ss v ss pd1:pd0 op amp gain v out0 1k ? 100 k ? 1k ? 100 k ? memory (32x16) dac0 and dac1 (vol) vref (vol) power-down (vol) gain (vol) status (vol) vref1:vref0 and pd1:pd0 vref1:vref0 and pd1:pd0 pd1:pd0 pd1:pd0 note 1: if internal band gap is selected, this buffer has a 2x gain, if the g bit = 1 , this is a total gain of 4. sck cs and control logic ( 1 ) ( 1 ) downloaded from: http:/// mcp48fvbxx ds20005466a-page 4 ? 2015 microchip technology inc. device features device # of channels resolution (bits) control interface dac output por/bor setting ( 1 ) # of v ref inputs internal band gap ? # of lat inputs memory specified operating range (v dd ) ( 2 ) MCP48FVB01 1 8 spi 7fh 1 yes 1 ram 1.8v to 5.5v mcp48fvb11 1 10 spi 1ffh 1 yes 1 ram 1.8v to 5.5v mcp48fvb21 1 12 spi 7ffh 1 yes 1 ram 1.8v to 5.5v mcp48fvb02 2 8 spi 7fh 1 yes 1 ram 1.8v to 5.5v mcp48fvb12 2 10 spi 1ffh 1 yes 1 ram 1.8v to 5.5v mcp48fvb22 2 12 spi 7ffh 1 yes 1 ram 1.8v to 5.5v mcp48feb01 1 8 spi 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp48feb11 1 10 spi 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp48feb21 1 12 spi 7ffh 1 yes 1 eeprom 1.8v to 5.5v mcp48feb02 2 8 spi 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp48feb12 2 10 spi 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp48feb22 2 12 spi 7ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47fvb01 1 8 i 2 c 7fh 1 yes 1 ram 1.8v to 5.5v mcp47fvb11 1 10 i 2 c 1ffh 1 yes 1 ram 1.8v to 5.5v mcp47fvb21 1 12 i 2 c 7ffh 1 yes 1 ram 1.8v to 5.5v mcp47fvb02 2 8 i 2 c 7fh 1 yes 1 ram 1.8v to 5.5v mcp47fvb12 2 10 i 2 c 1ffh 1 yes 1 ram 1.8v to 5.5v mcp47fvb22 2 12 i 2 c 7ffh 1 yes 1 ram 1.8v to 5.5v mcp47feb01 1 8 i 2 c 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb11 1 10 i 2 c 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb21 1 12 i 2 c 7ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb02 2 8 i 2 c 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb12 2 10 i 2 c 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb22 2 12 i 2 c 7ffh 1 yes 1 eeprom 1.8v to 5.5v note 1: factory default value. the dac output por/bor value can be modified via the n onvolatile dac output register(s) (available only on nonvolatile devices (mcp4xfebxx)). 2: analog output performance specified from 2.7v to 5.5v. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 5 mcp48fvbxx 1.0 electrical characteristics absolute maximum ratings (?) voltage on v dd with respect to v ss ......................................................................................................... -0.6v to +6.5v voltage on all pins with respect to v ss ............................................................................................... -0.6v to v dd +0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) .......................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd )...................................................................................................20 ma maximum current out of v ss pin (single) ..........................................................................................................50 ma (dual)...........................................................................................................100 ma maximum current into v dd pin (single) ..........................................................................................................50 ma (dual)...........................................................................................................100 ma maximum current sourced by the v out pin ............................................................................................................20 ma maximum current sunk by the v out pin..................................................................................................................20 ma maximum current sunk by the v ref pin .................................................................................................................125 a maximum input current source/sunk by sdi, sck, and cs pins .............................................................................2 ma maximum output current sunk by sdo output pin ................................................................................. ................25 ma total power dissipation ( 1 ) ............................................................................................................................... .....400 mw package power dissipation (t a = +50c, t j = +150c) msop-10 ........................................................................................................................ ..........................490 mw esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ????????????????????????????????????? 4 kv (hbm) ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????? 400v (mm) ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????????????????? ?????? ?? 1.5 kv (cdm) latch-up (per jedec jesd78a) @ +125c ......................................................................................... ............ 100 ma storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ........................................................................................ .......-55c to +125c soldering temperature of leads (10 seconds) .................................................................................... ................... +300c maximum junction temperature (t j ) .................................................................................................................... +150c note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd Cv oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:/// mcp48fvbxx ds20005466a-page 6 ? 2015 microchip technology inc. dc characteristics dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operati ng ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions supply voltage v dd 2.7 5.5 v 1.8 2.7 v dac operation (reduced analog specifications) and serial interface v dd voltage (rising) to ensure device power-on reset v por/bor 1.7 v ram retention voltage (v ram ) < v por v dd voltages greater than v por/bor limit ensure that device is out of reset. v dd rise rate to ensure power-on reset v ddrr ( note 3 ) v/ms high-voltage commands voltage range (hvc pin) v hv v ss 12.5 v the hvc pin will be at one of three input levels (v il , v ih or v ihh ) ( 1 ) high-voltage input entry voltage v ihhen 9.0 v threshold for entry into wiperlock technology - for compatibility with mcp48febxx devices high-voltage input exit voltage v ihhex v dd +0.8v v ( note 2 ) power-on reset to output-driven delay t pord 2 5 5 0 sv dd rising, v dd > v por note 1 this parameter is ensured by design. note 2 this parameter is ensured by characterization. note 3 por/bor voltage trip point is not slope dependent. hysteresis implemented with time delay. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 7 mcp48fvbxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions supply current i dd 320 a single 1mhz ( 2 ) serial interface active (not high-voltage command) vrxb:vrxa = 01 ( 6 ) v out is unloaded, v dd = 5.5v volatile dac register = 000h 910 a 10 mhz ( 2 ) 1.7 ma 20 mhz 510 a dual 1 mhz ( 2 ) 1 . 1m a 10 mhz ( 2 ) 1.85 ma 20 mhz 250 a single 1 mhz ( 2 ) serial interface active (not high-voltage command) vrxb:vrxa = 10 ( 4 ) v out is unloaded. v ref = v dd = 5.5v volatile dac register = 000h 840 a 10 mhz ( 2 ) 1 . 6 5m a 20 mhz ( 2 ) 380 a dual 1 mhz ( 2 ) 970 a 10 mhz ( 2 ) 1 . 7 5m a 20 mhz ( 2 ) 180 a single serial interface inactive ( 2 ) (not high-voltage command) vrxb:vrxa = 00 sck = sdi = v ss v out is unloaded. volatile dac register = 000h 380 a dual 180 a single serial interface inactive ( 2 ) (not high-voltage command) vrxb:vrxa = 11 , v ref = v dd sck = sdi = v ss v out is unloaded. volatile dac register = 000h 380 a dual 145 180 a single hvc = 12.5v (high-voltage command) serial interface inactive v ref = v dd = 5.5v, lat /hvc = v ihh dac registers = 000h v out pins are unloaded 260 400 a dual power-down current i ddp 0 . 6 53 . 8 a pdxb:pdxa = 01 ( 5 ) v out not connected note 2 this parameter is ensured by characterization. note 4 supply current is independent of current through the resistor ladder in mode vrxb:vrxa = 10 . note 5 the pdxb:pdxa = 01 , 10 , and 11 configurations should have the same current. note 6 by design, this is the worst-case current mode. downloaded from: http:/// mcp48fvbxx ds20005466a-page 8 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified op erating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions resistor ladder resistance r l 100 140 180 k ? 1.8v ? v dd ? 5.5v v ref ? 1.0v ( 7 ) resolution (# of resistors and # of taps) (see b.1 resolution ) n 256 taps 8-bit no missing codes 1024 ta ps 10-bit no missing codes 4096 ta ps 12-bit no missing codes nominal v out match ( 11 ) |v out - v outmean | /v outmean 0 . 51 . 0 % 2.7v ? v dd ? 5.5v ( 2 ) 1 . 2% 1.8v ( 2 ) v out te m p c o (see b.19 v out tem- perature coefficient ? v out / ? t 15 ppm/c code = mid-scale (7fh, 1ffh or 7ffh) v ref pin input voltage range v ref v ss v dd v 1.8v ? v dd ? 5.5v ( 1 ) note 1 this parameter is ensured by design. note 2 this parameter is ensured by characterization. note 7 resistance is defined as the resistance between the vref pin (mode vrxb:vrxa = 10 ) to vss pin. for dual-channel devices (mcp48fvbx2), this is the effective resistance of the each resistor ladder. the resistance measurement is that of the two resistor ladders measured in parallel. note 11 variation of one output voltage to mean output voltage. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 9 mcp48fvbxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified op erating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions zero-scale error (see b.5 zero-scale error (e zs ) ) (code = 000h) e zs 0.75 lsb 8-bit vrxb:vrxa = 11 , gx = 0 v ref = v dd , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 v dd = 5.5v, no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 , no load 3 lsb 10-bit vrxb:vrxa = 11 , gx = 0 v ref = v dd , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 v dd = 5.5v, no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 no load 12 lsb 12-bit vrxb:vrxa = 11 , gx = 0 v ref = v dd , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 v dd = 5.5v, no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 , no load see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 no load offset error (see b.8 offset error drift (e osd ) ) e osd -15 1.5 +15 mv vrxb:vrxa = 00 gx = 0 no load offset voltage temperature coefficient v ostc 1 0 v / c note 2 this parameter is ensured by characterization. downloaded from: http:/// mcp48fvbxx ds20005466a-page 10 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions full-scale error (see b.4 full-scale error (e fs ) ) e fs 4.5 lsb 8-bit code = ffh, vrxb:vrxa = 11 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 10 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 01 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 00 no load 18 lsb 10-bit code = 3ffh, vrxb:vrxa = 11 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 10 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 01 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 00 no load 70 lsb 12-bit code = fffh, vrxb:vrxa = 11 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 10 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 01 gx = 0 , v ref = 2.048v, no load see section 2.0, typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 00 no load note 2 this parameter is ensured by characterization. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 11 mcp48fvbxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operat ing ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions gain error (see b.9 gain error (e g ) ) ( 8 ) e g -1.0 0.1 +1.0 % of fsr 8-bit code = 250, no load vrxb:vrxa = 00 gx = 0 -1.0 0.1 +1.0 % of fsr 10-bit code = 1000, no load vrxb:vrxa = 00 gx = 0 -1.0 0.1 +1.0 % of fsr 12-bit code = 4000, no load vrxb:vrxa = 00 gx = 0 gain-error drift (see b.10 gain-error drift (e gd ) ) ? g/c -3 ppm/c note 8 this gain error does not include offset error. downloaded from: http:/// mcp48fvbxx ds20005466a-page 12 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions integral nonlinearity (see b.11 integral nonlinearity (inl) ) ( 10 ) inl -0.5 0.1 +0.5 lsb 8-bit vrxb:vrxa = 10 (codes: 6 to 250) v dd = v ref = 5.5v see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v v ref = 1.0v -1.5 0.4 +1.5 lsb 10-bit vrxb:vrxa = 10 (codes: 25 to 1000) v dd = v ref = 5.5v see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v v ref = 1.0v -6 1.5 +6 lsb 12-bit vrxb:vrxa = 10 (codes: 100 to 4000) v dd = v ref = 5.5v. see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v v ref = 1.0v note 2 this parameter is ensured by characterization. note 10 code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 13 mcp48fvbxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions differential nonlinearity (see b.12 differential nonlinearity (dnl) ) ( 10 ) dnl -0.25 0.0125 +0.25 lsb 8-bit vrxb:vrxa = 10 (codes: 6 to 250) v dd = v ref = 5.5v see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v -0.5 0.05 +0.5 lsb 10-bit vrxb:vrxa = 10 (codes: 25 to 1000) v dd = v ref = 5.5v see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v -1.0 0.2 +1.0 lsb 12-bit vrxb:vrxa = 10 (codes: 100 to 4000) v dd = v ref = 5.5v see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 01 v dd = 5.5v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 v ref = 1.0v, gx = 1 see section 2.0, typical performance curves ( 2 ) lsb v dd = 1.8v note 2 this parameter is ensured by characterization. note 10 code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000. downloaded from: http:/// mcp48fvbxx ds20005466a-page 14 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions -3 db bandwidth (see b.16 -3 db bandwidth ) bw 200 khz v ref = 2.048v 0.1v vrxb:vrxa = 10 , gx = 0 1 0 0 k h zv ref = 2.048v 0.1v vrxb:vrxa = 10 , gx = 1 output amplifier minimum output voltage v out(min) 0.01 v 1.8v ? v dd ? 5.5v output amplifiers minimum drive maximum output voltage v out(max) v dd C 0.04 v 1.8v ? v dd ? 5.5v output amplifiers maximum drive phase margin pm 66 degree () c l = 400 pf r l = ? slew rate ( 9 ) sr 0.44 v/s r l = 5 k ? short-circuit current i sc 3 9 14 ma dac code = full scale internal band gap band gap voltage v bg 1.18 1.22 1.26 v band gap voltage temperature coefficient v bgtc 1 5 p p m / c operating range (v dd ) 2.0 5.5 v v ref pin voltage stable 2.2 5.5 v v out output linear external reference (v ref ) input range ( 1 ) v ref v ss v dd C 0.04 v vrxb:vrxa = 11 (buffered mode) v ss v dd v vrxb:vrxa = 10 (unbuffered mode) input capacitance c ref 1 pf vrxb:vrxa = 10 (unbuffered mode) total harmonic distortion ( 1 ) thd -64 db v ref = 2.048v 0.1v vrxb:vrxa = 10 , gx = 0 frequency = 1 khz dynamic performance major code transition glitch (see b.14 major-code transition glitch ) 45 nv-s 1 lsb change around major carry 7ffh to 800h for 12-bit devices 1ffh to 200h for 10-bit devices 7fh to 80h for 8-bit devices digital feedthrough (see b.15 digital feedthrough ) < 1 0 n v - s note 1 this parameter is ensured by design. note 9 within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 15 mcp48fvbxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions digital inputs/outputs (cs , sck, sdi, sdo, lat0 /hvc) schmitt trigger high-input threshold v ih 0.45 v dd v2 . 7 v ? v dd ? 5.5v 0.5 v dd v1 . 8 v ? v dd ? 2.7v schmitt trigger low-input threshold v il 0 . 2 v dd v hysteresis of schmitt trigger inputs v hys 0 . 1 v dd v output low voltage v ol v ss 0 . 3 v dd v i ol = 5 ma, v dd = 5.5v v ss 0 . 3 v dd vi ol = 1 ma, v dd = 1.8v output high voltage v oh 0.7v dd v dd vi oh = -2.5 ma, v dd = 5.5v 0.7v dd v dd vi o h = -1 ma, v dd = 1.8v input leakage current i il -1 1 a v in = v dd and v in = v ss pin capacitance c in , c out 1 0p f f c = 20 mhz downloaded from: http:/// mcp48fvbxx ds20005466a-page 16 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operati ng ranges: v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions ram value value range n 0h ffh hex 8-bit 0h 3ffh hex 10-bit 0h fffh hex 12-bit dac register por/bor value n see table 4-2 hex 8-bit see table 4-2 hex 10-bit see table 4-2 hex 12-bit pdcon initial factory setting see table 4-2 hex power requirements power supply sensitivity (see b.17 power-supply sensitivity (pss) ) pss 0.002 0.005 %/% 8-bit code = 7fh 0.002 0.005 %/% 10-bit code = 1ffh 0.002 0.005 %/% 12-bit code = 7ffh downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 17 mcp48fvbxx dc notes: 1. this parameter is ensured by design. 2. this parameter is ensured by characterization. 3. por/bor voltage trip point is not slope dependent. hysteresis implemented with time delay. 4. supply current is independent of current through the resistor ladder in mode vrxb:vrxa = 10 . 5. the pdxb:pdxa = 01 , 10 , and 11 configurations should have the same current. 6. by design, this is the worst-case current mode. 7. resistance is defined as the resistance between the vref pin (mode vrxb:vrxa = 10 ) to vss pin. for dual-channel devices (mcp48fvbx2), this is the effective resistance of the each resistor ladder. the re sistance measurement is that of the two resistor ladders measured in parallel. 8. this gain error does not include offset error. 9. within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 10. code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000. 11. variation of one output voltage to mean output voltage. downloaded from: http:/// mcp48fvbxx ds20005466a-page 18 ? 2015 microchip technology inc. 1.1 reset, power-down, and spi mode timing waveforms and requirements figure 1-1: power-on and brown-out reset waveforms. figure 1-2: spi power-down command waveforms. table 1-1: reset and power-down timing timing characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified operating ranges: v dd = +1.8v to 5.5v, v ss = 0v r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions power-on reset delay t pord 60 s brown-out reset delay t bord 45 sv dd transitions from v dd(min) ? > v por v out driven to v out disabled power-down output disable time delay t pdd 10.5 s pdxb:pdxa = 11 , 10 , or 01 ? 00 started from falling edge of the sck at the end of the 24th clock cycle. volatile dac register = ffh, v out =10mv v out not connected power-down output enable time delay t pde 1 s pdxb:pdxa = 00 ? 11 , 10 , or 01 started from falling edge of the sck at the end of the 24th clock cycle v out = v out - 10 mv. v out not connected v dd t pord t bord v out v por (v bor ) v out at high z spi interface is operational 24th bit sck v out t pde t pdd (write command) 1st bit (next command) 24th bit (write command) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 19 mcp48fvbxx figure 1-3: v out settling time waveform. v out 0.5 lsb old value new value table 1-2: v out settling timing timing characteristics standard operating conditions (unless otherwise specified): operating temperature: -40c ? t a ? +125c (extended) unless otherwise noted, all parameters apply across these specified op erating ranges: v dd = +1.8v to 5.5v, v ss = 0v r l = 5 k ? from v out to v ss , c l = 100 pf typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions v out settling time (0.5lsb error band, c l = 100 pf) (see b.13 settling time ) t s 7 . 8 s8 - b i t code = 40h ? c0h; c0h ? 40h ( 3 ) 7.8 s 10-bit code = 100h ? 300h; 300h ? 100h ( 3 ) 7.8 s 12-bit code = 400h ? c00h; c00h ? 400h ( 3 ) note 3 within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). downloaded from: http:/// mcp48fvbxx ds20005466a-page 20 ? 2015 microchip technology inc. figure 1-4: spi timing (mode = 11 ) waveforms. figure 1-5: spi timing (mode = 00 ) waveforms. cs sck sdo sdi 70 71 72 73 74 77 80 msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 84 v ih v il v ih v ih v ihh v ih lat 0 0 1 1 94 96 96 97 98 note 1: the hvc pin is for signal voltage compatibility with mcp48febxx devices. hvc ( 1 ) cs sck sdo sdi 70 71 72 82 sdi 74 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 84 73 v ih v il v ih v ih v ihh v ih lat 0 0 1 1 94 96 96 97 98 note 1: the hvc pin is for signal voltage compatibility with mcp48febxx devices. hvc ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 21 mcp48fvbxx table 1-3: spi requirements (mode = 11 ) spi ac characteristics standard operating conditions (unless otherwise specified): operating temperature: -40 ? c ? t a ? +125 ? c (extended) operating voltage range is described in dc characteristics . param. no. sym. characteristic min. max. units conditions f sck sck input frequency 10 mhz v dd = 2.7v to 5.5v (read command) 20mhzv dd = 2.7v to 5.5v (all other commands) 1m h zv dd = 1.8v to 2.7v 70 tcsa2sch cs active (v il ) to commands 1st sck ? input 60 ns 71 tsch sck input high time 20 ns v dd = 2.7v to 5.5v 400 ns v dd = 1.8v to 2.7v 72 tscl sck input low time 20 ns v dd = 2.7v to 5.5v 400 ns v dd = 1.8v to 2.7v 73 tdiv2sch setup time of sdi input to sck ? edge 10 ns 74 tsch2dil hold time of sdi input from sck ? edge 20 ns 77 tcsh2 do zcs inactive (v ih ) to sdo output hi-impedance 50 ns note 1 80 tscl2dov sdo data output valid after sck ? edge 45 ns v dd = 2.7v to 5.5v 170 ns v dd = 1.8v to 2.7v 83 tsch2csl cs inactive (v ih ) after sck ? edge 100 ns v dd = 2.7v to 5.5v 1 s v dd = 1.8v to 2.7v 84 tcsh cs high time (v ih ) 50 ns 94 t latsu lat ? to sck (write data 24th bit) setup time 20 ns write data transferred ( 4 ) 96 t lat lat high or low time 20 ns 97 t hvcsu hvc ? to sck ? (1st data bit) (hvc setup time) 0n s high-voltage commands ( 1 ) (mcp48febxx only) 98 t hvchd sck (last bit of command (8th or 24th bit)) to hvc ? (hvc hold time) 25 ns high-voltage commands ( 1 ) (mcp48febxx only) note 1 this parameter is ensured by design. note 4 the transition of the lat signal must occur 10 ns before the rising edge of the 24th sck signal (spec 94) or the current register data value may not be transferred to the output latch (v out ) before the register is overwritten with the new value. downloaded from: http:/// mcp48fvbxx ds20005466a-page 22 ? 2015 microchip technology inc. table 1-4: spi requirements (mode = 00) spi ac characteristics standard operating conditions (unless otherwise specified): operating temperature: -40 ? c ? t a ? +125 ? c (extended) operating voltage range is described in dc characteristics . param. no. sym. characteristic min. max. units conditions f sck sck input frequency 10 mhz v dd = 2.7v to 5.5v (read command) 2 0m h zv dd = 2.7v to 5.5v (all other commands) 1m h zv dd = 1.8v to 2.7v 70 tcsa2sch cs active (v il ) to sck ? input 60 ns 71 tsch sck input high time 20 ns v dd = 2.7v to 5.5v 400 ns v dd = 1.8v to 2.7v 72 tscl sck input low time 20 ns v dd = 2.7v to 5.5v 400 ns v dd = 1.8v to 2.7v 73 t di v2sch setup time of sdi input to sck ? edge 10 ns 74 tsch2 di l hold time of sdi input from sck ? edge 20 ns 77 tcsh2 do zcs inactive (v ih ) to sdo output hi-impedance 50 ns note 1 80 tscl2 do v sdo data output valid after sck ? edge 45 ns v dd = 2.7v to 5.5v 170nsv dd = 1.8v to 2.7v 82 tssl2dov sdo data output valid after cs active (v il ) 7 0n s 83 tsch2csl cs inactive (v ih ) after sck ? edge 100 ns v dd = 2.7v to 5.5v 1 s v dd = 1.8v to 2.7v 84 tcsh cs high time (v ih ) 50 ns 94 t latsu lat ? to sck (write data 24th bit) setup time 10 ns write data transferred ( 4 ) 96 t lat lat high or low time 50 ns 97 t hvcsu hvc ? to sck ? (1st data bit) (hvc setup time) 0 ns high-voltage commands ( 1 ) (mcp48febxx only) 98 t hvchd sck ? (last bit of command (8th or 24th bit)) to hvc ? (hvc hold time) 25 ns high-voltage commands ( 1 ) (mcp48febxx only) note 1 this parameter is ensured by design. note 4 the transition of the lat signal must occur 10 ns before the rising edge of the 24th sck signal (spec 94) or the current register data value may not be transferred to the output latch (v out ) before the register is overwritten with the new value. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 23 mcp48fvbxx timing table notes: 1. this parameter is ensured by design. 2. this parameter ensured by characterization. 3. within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 4. the transition of the lat signal must occur 10 ns before the rising edge of the 24th sck signal (spec 94) or the current register data value may not be transferred to the output latch (v out ) before the register is overwritten with the new value. downloaded from: http:/// mcp48fvbxx ds20005466a-page 24 ? 2015 microchip technology inc. temperature specifications electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c note 1 storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 10ld-msop ? ja 202 c/w note 1: the mcp48fvbxx devices operate over this extended temperature range, but with reduced performance. operation in this range must not cause t j to exceed the maximum junction temperature of +150c. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 25 mcp48fvbxx 2.0 typical performance curves note: the device performance curves are available in a separate document. this is done to keep the file size of this pdf document less than the 10 mb file attachment limit of many mail servers. the mcp48fxbxx performance curves document is literature number ds20005440 , and can be found on the microchip website. look on the mcp48fvbxx product page under documentation and software, in the data sheets category. downloaded from: http:/// mcp48fvbxx ds20005466a-page 26 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 27 mcp48fvbxx 3.0 pin descriptions overviews of the pin functions are provided in sections 3.1, positive power supply input (vdd) through 3.10, spi - serial clock pin (sck) . the descriptions of the pins for the single-dac output device are listed in ta bl e 3 - 1 , and descriptions for the dual-dac output device are listed in ta bl e 3 - 2 . table 3-1: mcp48fvbx1 (singl e-dac) pinout description pin msop-10ld symbol i/o buffer type standard function 1v dd p supply voltage pin 2c s i st spi chip select pin 3v ref0 a analog voltage reference input pin 4v out0 a analog buffered analog voltage output pin 5 nc not internally connected 6l a t 0 /hvc i hv st dac register latch/high-voltage command pin. latch pin allows the value in the serial shift register to transfer to the volatile dac register. (the hvc signal is present to indicate voltage level compatibility with the nonvolatile device family (mcp48febxx)). 7v ss p ground reference pin for all circuitries on the device 8 sdo o spi serial data output pin 9 sck i st spi serial clock pin 10 sdi i st spi serial data input pin legend: a = analog st = schmitt trigger hv = high voltage i = input o = output i/o = input/output p = power table 3-2: mcp48fvbx2 (dual -dac) pinout description pin msop-10ld symbol i/o buffer type standard function 1v dd p supply voltage pin 2c s i st spi chip select pin 3v ref a analog voltage reference input pin (for dac0 and dac1) 4v out0 a analog buffered analog voltage output 0 pin 5v out1 a analog buffered analog voltage output 1 pin 6l a t /hvc i hv st dac register latch/high-voltage command pin. latch pin allows the value in the serial shift register to transfer to the volatile dac register (for dac0 and dac1). (the hvc signal is present to indicate voltage level compatibility with the nonvolatile device family (mcp48febxx)). 7v ss p ground reference pin for all circuitries on the device 8 sdo o spi serial data output pin 9 sck i st spi serial clock pin 10 sdi i st spi serial data input pin legend: a = analog st = schmitt trigger hv = high voltage i = input o = output i/o = input/output p = power downloaded from: http:/// mcp48fvbxx ds20005466a-page 28 ? 2015 microchip technology inc. 3.1 positive power supply input (v dd ) v dd is the positive supply voltage input pin. the input supply voltage is relative to v ss . the power supply at the v dd pin should be as clean as possible for a good dac performance. it is recommended to use an appropriate bypass capacitor of about 0.1 f (ceramic) to ground. an additional 10 f capacitor (tantalum) in parallel is also recommended to further attenuate noise present in application boards. 3.2 voltage reference pin (v ref ) the v ref pin is either an input or an output. when the dacs voltage reference is configured as the v ref pin, the pin is an input. when the dacs voltage reference is configured as the internal band gap, the pin is an output. when the dacs voltage reference is configured as the v ref pin, there are two options for this voltage input: v ref pin voltage buffered v ref pin voltage unbuffered the buffered option is offered in cases where the external reference voltage does not have sufficient current capability to not drop its voltage when connected to the internal resistor ladder circuit. when the dacs voltage reference is configured as the device v dd , the v ref pin is disconnected from the internal circuit. when the dacs voltage reference is configured as the internal band gap, the v ref pins drive capability is minimal, so the output signal should be buffered. see section 5.2, voltage reference selection and register 4-2 for more details on the configuration bits. 3.3 analog output voltage pin (v out ) v out is the dac analog voltage output pin. the dac output has an output amplifier. the dac output range is dependent on the selection of the voltage reference source (and potential output gain selection). these are: device v dd - the full-scale range of the dac output is from v ss to approximately v dd . v ref pin - the full-scale range of the dac output is from v ss to g ? v rl , where g is the gain selection option (1x or 2x). internal band gap - the full-scale range of the dac output is from v ss to g ? (2 ? v bg ), where g is the gain selection option (1x or 2x). in normal mode, the dc impedance of the output pin is about 1 ? . in power-down mode, the output pin is internally connected to a known pull-down resistor of 1k ? , 100 k ? , or open. the power-down selection bits settings are shown in register 4-3 and ta b l e 5 - 5 . 3.4 no connect (nc) the nc pin is not connected to the device. 3.5 ground (v ss ) the v ss pin is the device ground reference. the user must connect the v ss pin to a ground plane through a low-impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.6 latch pin (lat )/high-voltage command (hvc) the lat pin is used to force the transfer of the dac registers shift register to the dac output register. this allows dac outputs to be updated at the same time. the update of the vrxb:vrxa, pdxb:pdxa and gx bits are also controlled by the lat pin state. the pin is compatible with hvc voltage levels that are used for the nonvolatile mcp48febxx devices. 3.7 spi - chip select pin (cs ) the cs pin enables/disables the serial interface. the serial interface must be enabled for the spi commands to be received by the device. refer to section 6.2, spi serial interface for more details of spi serial interface communication. 3.8 spi - serial data in pin (sdi) the sdi pin is the serial data input pin of the spi interface. the sdi pin is used to write the dac registers and configuration bits. refer to section 6.2, spi serial interface for more details on spi serial interface communication. 3.9 spi - serial data out pin (sdo) the sdo pin is the serial data output pin of the spi interface. the sdo pin is used to read the dac registers and configuration bits. refer to section 6.2, spi serial interface for more details on spi serial interface communication. 3.10 spi - serial clock pin (sck) the sck pin is the serial clock pin of the spi interface. the mcp48fvbxx spi interface only accepts external serial clocks. refer to section 6.2, spi serial interface for more details on spi serial interface communication. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 29 mcp48fvbxx 4.0 general description the mcp48fvbx1 (MCP48FVB01, mcp48fvb11, and mcp48fvb21) devices are single-channel voltage output devices. the mcp48fvbx2 (mcp48fvb02, mcp48fvb12, and mcp48fvb22) devices are dual-channel voltage output devices. these devices are offered with 8-bit (mcp48fvb0x), 10-bit (mcp48fvb1x) and 12-bit (mcp48fvb2x) resolution and include volatile memory, an spi serial interface and a write latch (lat ) pin to control the update of the written dac value to the dac output pin. the devices use a resistor ladder architecture. the resistor ladder dac is driven from a software-selectable voltage reference source. the source can be either the devices internal v dd , an external v ref pin voltage (buffered or unbuffered) or an internal band gap voltage source. the dac output is buffered with a low-power, precision output amplifier (op amp). this output amplifier provides a rail-to-rail output with low offset voltage and low noise. the gain (1x or 2x) of the output buffer is software configurable. the devices operate from a single supply voltage. this voltage is specified from 2.7v to 5.5v for full specified operation, and from 1.8v to 5.5v for digital operation. the devices operate between 1.8v and 2.7v, but some device parameters are not specified. the main functional blocks are: power-on reset/brown-out reset (por/bor) device memory resistor ladder output buffer/v out operation internal band gap (as a voltage reference ) spi serial interface module 4.1 power-on reset/brown-out reset (por/bor) the internal power-on reset (por)/brown-out reset (bor) circuit monitors the power supply voltage (v dd ) during operation. this circuit ensures correct device start-up at system power-up and power-down events. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less than 1.8v. por occurs as the voltage is rising (typically from 0v), while bor occurs as the voltage is falling (typically from v dd(min) or higher). the por and bor trip points are at the same voltage, and the condition is determined by whether the v dd voltage is rising or falling (see figure 4-1 ). what occurs is different depending on whether the reset is a por or a bor. when v por /v bor ? 2015 microchip technology inc. ds20005466a-page 31 mcp48fvbxx 4.2 device memory user memory includes two types of memory: volatile register memory (ram) device configuration memory each memory address is 16 bits wide.the memory mapped register space is shown in tab le 4 - 1 . (see section 4.2.2, device configuration memory ). 4.2.1 volatile register memory (ram) there are up to five volatile memory locations: dac0 and dac1 output value registers v ref select register power-down configuration register gain and status register the volatile memory starts functioning when the device v dd is at (or above) the ram retention voltage (v ram ). the volatile memory will be loaded with the default device values when the v dd rises across the v por /v bor voltage trip point. table 4-1: memory map (x16) address function address function 00h volatile dac0 register 10h reserved ( 1 , 2 ) 01h volatile dac1 register 11h reserved ( 1 , 2 ) 02h reserved ( 1 ) 12h reserved ( 1 , 2 ) 03h reserved ( 1 ) 13h reserved ( 1 , 2 ) 04h reserved ( 1 ) 14h reserved ( 1 , 2 ) 05h reserved ( 1 ) 15h reserved ( 1 , 2 ) 06h reserved ( 1 ) 16h reserved ( 1 , 2 ) 07h reserved ( 1 ) 17h reserved ( 1 , 2 ) 08h v ref register 18h reserved ( 1 , 2 ) 09h power-down register 19h reserved ( 1 , 2 ) 0ah gain and status register 1ah reserved ( 1 , 2 ) 0bh reserved ( 1 ) 1bh reserved ( 1 , 2 ) 0ch reserved ( 1 ) 1ch reserved ( 1 , 2 ) 0dh reserved ( 1 ) 1dh reserved ( 1 , 2 ) 0eh reserved ( 1 ) 1eh reserved ( 1 , 2 ) 0fh reserved ( 1 ) 1fh reserved ( 1 , 2 ) volatile memory address range nonvolatile memory address range note 1: reading a reserved memory location will result in the spi command command error condition. the sdo pin will output all 0s. forcing the cs pin to the v ih state will reset the spi interface. 2: nonvolatile memory address range is shown to reflect memory map compatibility with the mcp48febxx family of devices. downloaded from: http:/// mcp48fvbxx ds20005466a-page 32 ? 2015 microchip technology inc. 4.2.2 device configuration memory the status register is described in register 4-4 . 4.2.3 unimplemented register bits read commands of a valid location will read unimplemented bits as 0 . 4.2.4 unimplemented (reserved) locations normal (voltage) commands (read or write) to any unimplemented memory address (reserved) will result in a command error condition (cmderr). read commands of a reserved location will read bits as 1 . 4.2.4.1 default factory por memory state table 4-2 shows the default factory por initialization of the device memory map for the 8-, 10- and 12-bit devices. table 4-2: factory default por / bor values address function por/bor value address function por/bor value 8-bit 10-bit 12-bit 8-bit 10-bit 12-bit 00h volatile dac0 register 7fh 1ffh 7ffh 10h reserved ( 1 , 2 ) ffh 3ffh fffh 01h volatile dac1 register 7fh 1ffh 7ffh 11h reserved ( 1 , 2 ) ffh 3ffh fffh 02h reserved ( 1 ) ffh 3ffh fffh 12h reserved ( 1 , 2 ) ffh 3ffh fffh 03h reserved ( 1 ) ffh 3ffh fffh 13h reserved ( 1 , 2 ) ffh 3ffh fffh 04h reserved ( 1 ) ffh 3ffh fffh 14h reserved ( 1 , 2 ) ffh 3ffh fffh 05h reserved ( 1 ) ffh 3ffh fffh 15h reserved ( 1 , 2 ) ffh 3ffh fffh 06h reserved ( 1 ) ffh 3ffh fffh 16h reserved ( 1 , 2 ) ffh 3ffh fffh 07h reserved ( 1 ) ffh 3ffh fffh 17h reserved ( 1 , 2 ) ffh 3ffh fffh 08h v ref register 0000h 0000h 0000h 18h reserved ( 1 , 2 ) ffh 3ffh fffh 09h power-down register 0000h 0000h 0000h 19h reserved ( 1 , 2 ) ffh 3ffh fffh 0ah gain and status register 0080h 0080h 0080h 1ah reserved ( 1 , 2 ) ffh 3ffh fffh 0bh reserved ( 1 ) ffh 3ffh fffh 1bh reserved ( 1 , 2 ) ffh 3ffh fffh 0ch reserved ( 1 ) ffh 3ffh fffh 1ch reserved ( 1 , 2 ) ffh 3ffh fffh 0dh reserved ( 1 ) ffh 3ffh fffh 1dh reserved ( 1 , 2 ) ffh 3ffh fffh 0eh reserved ( 1 ) ffh 3ffh fffh 1eh reserved ( 1 , 2 ) ffh 3ffh fffh 0fh reserved ( 1 ) ffh 3ffh fffh 1fh reserved ( 1 , 2 ) ffh 3ffh fffh volatile memory address range nonvolatile memory address range note 1: reading a reserved memory location will result in the spi command command error condition. the sdo pin will output all 0 s. forcing the cs pin to the v ih state will reset the spi interface. 2: nonvolatile memory address range is shown to reflect memory map compatibility with the mcp48febxx family of devices. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 33 mcp48fvbxx 4.2.5 device registers register 4-1 shows the format of the dac output value registers. these registers will be either 8 bits, 10 bits, or 12 bits wide. the values are right justified. register 4-1: dac0 and dac1 registers u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 12-bit d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 10-bit ( 1 ) ( 1 ) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 8-bit ( 1 ) ( 1 ) ( 1 ) ( 1 ) d07 d06 d05 d04 d03 d02 d01 d00 bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown = 12-bit device = 10-bit device = 8-bit device 12-bit 10-bit 8-bit bit 15-12 bit 15-10 bit 15-8 unimplemented: read as 0 bit 11-0 d11-d00: dac output value - 12-bit devices fffh =full-scale output value 7ffh =mid-scale output value 000h =zero-scale output value bit 9-0 d09-d00: dac output value - 10-bit devices 3ffh =full-scale output value 1ffh =mid-scale output value 000h =zero-scale output value b i t 7 - 0 d07-d00: dac output value - 8-bit devices ffh =full-scale output value 7fh =mid-scale output value 000h =zero-scale output value note 1: unimplemented bit, read as 0 . downloaded from: http:/// mcp48fvbxx ds20005466a-page 34 ? 2015 microchip technology inc. register 4-2 shows the format of the voltage reference control register. each dac has two bits to control the source of the voltage reference of the dac. register 4-2: voltage reference (vre f) control register (address 08h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 single ( 1 ) ( 1 ) vr0b vr0a dual vr1b vr1a vr0b vr0a bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown = single-channel device = dual-channel device single dual bit 15-2 bit 15-4 unimplemented: read as 0 bit 1-0 bit 3-0 vrxb-vrxa: dac voltage reference control bits 11 =v ref pin (buffered); v ref buffer enabled 10 =v ref pin (unbuffered); v ref buffer disabled 01 =internal band gap (1.22v typical); v ref buffer enabled v ref voltage driven when powered-down 00 =v dd (unbuffered); v ref buffer disabled. use this state with power-down bits for lowest current. note 1: unimplemented bit, read as 0 . downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 35 mcp48fvbxx register 4-3 shows the format of the power-down control register. each dac has two bits to control the power-down state of the dac. register 4-3: power-down control register (address 09h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 single ( 1 ) ( 1 ) pd0b pd0a dual pd1b pd1a pd0b pd0a bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-2 bit 15-4 unimplemented: read as 0 bit 1-0 bit 3-0 pdxb-pdxa: dac power-down control bits ( 2 ) 11 =powered down - v out is open circuit. 10 =powered down - v out is loaded with a 100 k ? resistor to ground. 01 =powered down - v out is loaded with a 1 k ? resistor to ground. 00 =normal operation (not powered-down) note 1: unimplemented bit, read as 0 . 2: see table 5-5 and figure 5-10 for more details. downloaded from: http:/// mcp48fvbxx ds20005466a-page 36 ? 2015 microchip technology inc. register 4-4 shows the format of the volatile gain control and system status register. each dac has one bit to control the gain of the dac and three status bits. register 4-4: gain control and system status register (address 0ah ) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 single ( 1 ) g0 por dual g1 g0 por bit 15 bit 0 legend: r = readable bit w = writable bit c = clear able bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown = single-channel device = dual-channel device single dual bit 15-9 bit 15-10 unimplemented: read as 0 bit 9 g1: dac1 output driver gain control bits ( dual-channel device only ) 1 =2x gain 0 =1x gain bit 8 bit 8 g0: dac0 output driver gain control bits 1 =2x gain 0 =1x gain bit 7 bit 7 por: power-on reset (brown-out reset) status bit this bit indicates if a power-on reset (por) or brown-out reset (bor) event has occurred since the last read command of this register. reading this register clears the state of the por status bit. 1 = a por (bor) event occurred since the last read of this register. reading this register clears this bit. 0 = a por (bor) event has not occurred since the last read of this register. bit 6-0 bit 6-0 unimplemented: read as 0 note 1: unimplemented bit, read as 0 . downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 37 mcp48fvbxx 5.0 dac circuitry the digital-to-analog converter circuitry converts a digital value into its analog representation. the description details the functional operation of the device. the dac circuit uses a resistor ladder implementation. devices have up to two dacs. figure 5-1 shows the functional block diagram for the mcp48fvbxx dac circuitry. the functional blocks of the dac include: resistor ladder voltage reference selection output buffer/v out operation internal band gap (as a voltage reference) latch pin (lat ) power-down operation figure 5-1: mcp48fvbxx dac module block diagram. r s(2) v ref + - dac output r s(1) r s(2 n - 1) r s(2 n - 2) r s(2 n - 3) r s(2 n ) + - v dd v rl gain (1x or 2x) v out 1 k ? 100 k ? pd1:pd0 v dd pd1:pd0 v dd pd1:pd0 and pd1:pd0 vref1:vref0 v w r rl (~140 k ? ) band gap (1.22v typical) v dd vref1:vref0 pd1:pd0 and bgen selection internal band gap voltage reference selection resistor ladder power-down operation power-down operation power-down operation a (rl) b vref1:vref0 where: # of resistors in resistor ladder = 256 ( mcp48fvb0x ) = 1024 ( mcp48fvb1x ) = 4096 ( mcp48fvb2x ) v w dac register value # of resistors in resistor ladder ------------------------------------------------------------------------------ v rl ? = output buffer/v out operation downloaded from: http:/// mcp48fvbxx ds20005466a-page 38 ? 2015 microchip technology inc. 5.1 resistor ladder the resistor ladder is a digital potentiometer with the b terminal internally grounded and the a terminal connected to the selected reference voltage (see figure 5-2 ). the volatile dac register controls the wiper position. the wiper voltage (v w ) is proportional to the dac register value divided by the number of resistor elements (r s ) in the ladder (256, 1024 or 4096) related to the v rl voltage. the output of the resistor network will drive the input of an output buffer. the resistor network is made up of these three parts: resistor ladder (string of r s elements) wiper switches dac register decode the resistor ladder (r rl ) has a typical impedance of approximately 140 k ? . this resistor ladder resistance (r rl ) may vary from device to device by up to 20%. since this is a voltage divider configuration, the actual r rl resistance does not affect the output given a fixed voltage at v rl . equation 5-1 shows the calculation for the step resistance: equation 5-1: r s calculation if the unbuffered v ref pin is used as the v rl voltage source, this voltage source should have a low output impedance. when the dac is powered-down, the resistor ladder is disconnected from the selected reference voltage. figure 5-2: resistor ladder model block diagram. note: the maximum wiper position is 2 n C1, while the number of resistors in the resistor ladder is 2 n . this means that when the dac register is at full-scale, there is one resistor element (r s ) between the wiper and the v rl voltage. r s r rl 256 ?? ------------- = r s r rl 1024 ?? ---------------- = 8-bit device 10-bit device r s r rl 4096 ?? ---------------- = 12-bit device r s(2 n ) r s(2 n - 1) r s(2 n - 2) r s(1) 2 n - 1 2 n - 2 10 r rl v rl v w dac register pd1:pd0 analog mux r w r w r w r w where: # of resistors in resistor ladder = 256 ( mcp48fvb0x ) = 1024 ( mcp48fvb1x ) = 4096 ( mcp48fvb2x ) v w dac register value # of resistors in resistor ladder ------------------------------------------------------------------------------ v rl ? = note 1: the analog switch resistance (r w ) does not affect performance due to the voltage divider configuration. ( 1 ) ( 1 ) ( 1 ) ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 39 mcp48fvbxx 5.2 voltage reference selection the resistor ladder has up to four sources for the reference voltage. two user control bits (vref1:vref0) are used to control the selection, with the selection connected to the v rl node (see figures 5-3 and 5-4 ). the four voltage source options for the resistor ladder are: 1. v dd pin voltage 2. internal voltage reference (v bg ) 3. v ref pin voltage unbuffered 4. v ref pin voltage internally buffered the selection of the voltage is specified with the volatile vref1:vref0 configuration bits (see register 4-2 ). on a por/bor event, the default state of the configuration bits is latched into the volatile vref1:vref0 configuration bits. when the user selects the v dd as reference, the v ref pin voltage is not connected to the resistor ladder. if the v ref pin is selected, then a selection has to be made between the buffered or unbuffered mode. 5.2.1 unbuffered mode the v ref pin voltage may be from v ss to v dd . 5.2.2 buffered mode the v ref pin voltage may be from 0.01v to v dd C 0.04v. the input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and frequency response. figure 5-3: resistor ladder reference voltage selection block diagram. figure 5-4: reference voltage selection implementation block diagram. 5.2.3 band gap mode if the internal band gap is selected, then the external v ref pin should not be driven and only use high-impedance loads. decoupling capacitors are recommended for optimal operation. the band gap output is buffered, but the internal switches limit the current that the output should source to the v ref pin. the resistor ladder buffer is used to drive the band gap voltage for the cases of multiple dac outputs. this ensures that the resistor ladders are always properly sourced when the band gap is selected. note 1: the voltage source should have a low output impedance. if the voltage source has a high output impedance, then the voltage on the v ref pin would be lower than expected. the resistor ladder has a typical impedance of 140 k ? and a typical capacitance of 29 pf. 2: if the v ref pin is tied to the v dd voltage, v dd mode (vref1:vref0 = 00 ) is recommended. note 1: any variation or noises on the reference source can directly affect the dac output. the reference voltage needs to be as clean as possible for accurate dac performance. 2: if the v ref pin is tied to the v dd voltage, v dd mode (vref1:vref0 = 00 ) is recommended. v rl v dd buffer reference vref1:vref0 selection v ref band gap v ref + - v dd v dd pd1:pd0 and vref1:vref0 band gap (1.22v typical) v dd vref1:vref0 pd1:pd0 v rl note 1: the band gap voltage (v bg ) is 1.22v typical. the band gap output goes through the buffer with a 2x gain to create the v rl voltage. see section 5.4, internal band gap for additional information on the band gap circuit. vref1:vref0 and bgen ( 1 ) downloaded from: http:/// mcp48fvbxx ds20005466a-page 40 ? 2015 microchip technology inc. 5.3 output buffer/v out operation the output driver buffers the wiper voltage (v w ) of the resistor ladder. the dac output is buffered with a low-power, precision output amplifier (op amp). this amplifier provides a rail-to-rail output with low offset voltage and low noise. the amplifiers output can drive the resistive and high-capacitive loads without oscillation. the amplifier provides a maximum load current which is enough for most programmable voltage reference applications. refer to section 1.0, electrical characteristics for the specifications of the output amplifier. figure 5-5 shows the block diagram of the output driver circuit. the user can select the output gain of the output amplifier. the gain options are: a) gain of 1, with either the v dd or v ref pin used as reference voltage. b) gain of 2. power-down logic also controls the output buffer operation (see section 5.6, power-down operation ) for additional information on power-down. in any of the three power-down modes, the op amp is powered-down and its output becomes a high impedance to the v out pin. table 5-1 shows the gain bit operation. figure 5-5: output driver block diagram. 5.3.1 programmable gain the amplifiers gain is controlled by the gain (g) configuration bit (see register 4-4 ) and the v rl reference selection (see section 5.2, voltage reference selection ). the volatile g bit value can be modified by: por events bor events spi write commands note: the load resistance must be kept higher than 5 k ? for stable and expected analog output (to meet electrical specifications). table 5-1: output driver gain gain bit gain comment 0 1 1 2 limits v ref pin voltages relative to device v dd voltage. + - gain v out 1 k ? 100 k ? pd1:pd0 v dd pd1:pd0 v w note 1: gain options are 1x and 2x. ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 41 mcp48fvbxx 5.3.2 output voltage the volatile dac register values, along with the device configuration bits, control the analog v out voltage. the volatile dac registers value is unsigned binary. the formula for the output voltage is given in equation 5-2 . ta b l e 5 - 3 shows examples of volatile dac register values and the corresponding theoretical v out voltage for the mcp48fvbxx devices. equation 5-2: calculating output voltage (v out ) the following events update the dac register value and therefore the analog voltage output (v out ): power-on reset brown-out reset write command the v out voltage will start driving to the new value after any of these events has occurred. 5.3.3 step voltage (v s ) the step voltage is dependent on the device resolution and the calculated output voltage range. 1 lsb is defined as the ideal voltage difference between two successive codes. the step voltage can easily be calculated by using equation 5-3 . theoretical step voltages are shown in ta b l e 5 - 2 for several v ref voltages. equation 5-3: v s calculation note: when gain = 2 (v rl = v ref ) and if v ref > v dd / 2, the v out voltage will be limited to v dd . so if v ref = v dd , then the v out voltage will not change for volatile dac register values mid-scale and greater, since the op amp is at full-scale output. where: # of resistors in resistor ladder = 4096 ( mcp48fvb2x ) = 1024 ( mcp48fvb1x ) =256 ( mcp48fvb0x ) v out v rl dac register value ? # of resistors in resistor ladder ------------------------------------------------------------------------------ g a i n ? = table 5-2: theoretical step voltage (v s ) ( 1 ) v ref 5.0 2.7 1.8 1.5 1.0 v s 1.22 mv 659 v 439 v 366 v 244 v 12-bit 4.88 mv 2.64 mv 1.76 mv 1.46 mv 977 v 10-bit 19.5 mv 10.5 mv 7.03 mv 5.86 mv 3.91 mv 8-bit note 1: when gain = 1x, v fs = v rl , and v zs = 0v. where: # of resistors in resistor ladder = 4096 ( 12-bit ) = 1024 ( 10-bit ) = 256 ( 8-bit ) v s v rl # of resistors in resistor ladder ------------------------------------------------------------------------------ g a i n ? = downloaded from: http:/// mcp48fvbxx ds20005466a-page 42 ? 2015 microchip technology inc. 5.3.4 output slew rate figure 5-6 shows an example of the slew rate of the v out pin. the slew rate can be affected by the characteristics of the circuit connected to the v out pin. figure 5-6: v out pin slew rate. 5.3.4.1 small capacitive load with a small capacitive load, the output buffers current is not affected by the capacitive load (c l ). but still, the v out pins voltage is not a step transition from one output value (dac register value) to the next output value. the change of the v out voltage is limited by the output buffers characteristics, so the v out pin voltage will have a slope from the initial voltage to the new voltage. this slope is fixed for the output buffer, and is referred to as the buffer slew rate (sr buf ). 5.3.4.2 large capacitive load with a larger capacitive load, the slew rate is determined by two factors: the output buffers short-circuit current (i sc ) the v out pins external load i out cannot exceed the output buffers short-circuit current (i sc ), which fixes the output buffer slew rate (sr buf ). the voltage on the capacitive load (c l ), v cl , changes at a rate proportional to i out , which fixes a capacitive load slew rate (sr cl ). the v cl voltage slew rate is limited to the slower of the output buffers internally set slew rate (sr buf ) and the capacitive load slew rate (sr cl ). 5.3.5 driving resistive and capacitive loads the v out pin can drive up to 100 pf of capacitive load in parallel with a 5 k ? resistive load (to meet electrical specifications). a v out vs. resistive load characterization graph is provided in the typical performance curves for this device (see mcp48fxbxx - typical performance curves ds20005440 ). v out drops slowly as the load resistance decreases after about 3.5 k ? . it is recommended to use a load with r l greater than 5 k ? . driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loops phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response with overshoot and ringing in the step response. that is, since the v out pins voltage does not quickly follow the buffers input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. this causes voltage ringing on the v out pin. when driving large capacitive loads with the output buffer, a small series resistor (r iso ) at the output (see figure 5-7 ) improves the output buffers stability (feedback loops phase margin) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 5-7: circuit to stabilize output buffer for large capacitive loads (c l ). the r iso resistor value for your circuit needs to be selected. the resulting frequency response peaking and step response overshoot for this r iso resistor value should be verified on the bench. modify the r iso s resistance value until the output characteristics meet your requirements. a method to evaluate the systems performance is to inject a step voltage on the v ref pin and observe the v out pins characteristics. time dacx = a v out v out(a) v out(b) dacx= b slew rate v out b ?? v out a ?? ? ? t -------------------------------------------------- = note: additional insight into circuit design for driving capacitive loads can be found in an884 C ?driving capacitive loads with op amps? (ds00884). v out op amp v w c l r iso r l v cl downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 43 mcp48fvbxx table 5-3: dac input code vs. calculated analog output (v out ) (v dd = 5.0v) device volatile dac register value v rl ( 1 ) lsb gain selection ( 2 ) v out ( 3 ) equation v equation v mcp48fvb2x (12-bit) 1111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (4095/4096) ? 1 4.998779 2.5v 2.5v/4096 610.4 1x v rl ? (4095/4096) ? 1 2.499390 2x ( 2 ) v rl ? (4095/4096) ? 2) 4.998779 0111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (2047/4096) ? 1) 2.498779 2.5v 2.5v/4096 610.4 1x v rl ? (2047/4096) ? 1) 1.249390 2x ( 2 ) v rl ? (2047/4096) ? 2) 2.498779 0011 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (1023/4096) ? 1) 1.248779 2.5v 2.5v/4096 610.4 1x v rl ? (1023/4096) ? 1) 0.624390 2x ( 2 ) v rl ? (1023/4096) ? 2) 1.248779 0000 0000 0000 5.0v 5.0v/4096 1,220.7 1x v rl * (0/4096) ? 1) 0 2.5v 2.5v/4096 610.4 1x v rl * (0/4096) ? 1) 0 2x ( 2 ) v rl * (0/4096) ? 2) 0 mcp48fvb1x (10-bit) 11 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (1023/1024) ? 1 4.995117 2.5v 2.5v/1024 2,441.4 1x v rl ? (1023/1024) ? 1 2.497559 2x ( 2 ) v rl ? (1023/1024) ? 2 4.995117 01 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (511/1024) ? 1 2.495117 2.5v 2.5v/1024 2,441.4 1x v rl ? (511/1024) ? 1 1.247559 2x ( 2 ) v rl ? (511/1024) ? 2 2.495117 00 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (255/1024) ? 1 1.245117 2.5v 2.5v/1024 2,441.4 1x v rl ? (255/1024) ? 1 0.622559 2x ( 2 ) v rl ? (255/1024) ? 21 . 2 4 5 1 1 7 00 0000 0000 5.0v 5.0v/1024 4,882.8 1x v rl ? (0/1024) ? 1 0 2.5v 2.5v/1024 2,441.4 1x v rl ? (0/1024) ? 1 0 2x ( 2 ) v rl ? (0/1024) ? 10 mcp48fvb0x (8-bit) 1111 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (255/256) ? 1 4.980469 2.5v 2.5v/256 9,765.6 1x v rl ? (255/256) ? 1 2.490234 2x ( 2 ) v rl ? (255/256) ? 2 4.980469 0111 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (127/256) ? 1 2.480469 2.5v 2.5v/256 9,765.6 1x v rl ? (127/256) ? 1 1.240234 2x ( 2 ) v rl ? (127/256) ? 2 2.480469 0011 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (63/256) ? 1 1.230469 2.5v 2.5v/256 9,765.6 1x v rl ? (63/256) ? 1 0.615234 2x ( 2 ) v rl ? (63/256) ? 2 1.230469 0000 0000 5.0v 5.0v/256 19,531.3 1x v rl ? (0/256) ? 1 0 2.5v 2.5v/256 9,765.6 1x v rl ? (0/256) ? 1 0 2x ( 2 ) v rl ? (0/256) ? 20 note 1: v rl is the resistor ladders reference voltage. it is independent of vref1:vref0 selection. 2: gain selection of 2x (gx = 1 ) requires voltage reference source to come from v ref pin (vref1:vref0 = 10 or 11 ) and requires v ref pin voltage (or v rl ) v dd /2, or from the internal band gap (vref1:vref0 = 01 ). 3: these theoretical calculations do not take into account the offset, gain and nonlinearity errors. downloaded from: http:/// mcp48fvbxx ds20005466a-page 44 ? 2015 microchip technology inc. 5.4 internal band gap the internal band gap is designed to drive the resistor ladder buffer. the resistance of a resistor ladder (r rl ) is targeted to be 140 k ? ( ? 40 k ? ), which means a minimum resistance of 100 k ? . the band gap selection can be used across the v dd voltages while maximizing the v out voltage ranges. for v dd voltages below the 2 ? gain ? v bg voltage, the output for the upper codes will be clipped to the v dd voltage. table 5-4 shows the maximum dac register code given device v dd and gain bit setting. table 5-4: v out using band gap v dd dac gain max dac code ( 1 ) 12-bit 10-bit 8-bit comment 5.5 1 fffh 3ffh ffh v out(max) = 2.44v ( 2 ) 2 fffh 3ffh ffh v out(max) = 4.88v ( 2 ) 2.7 1 fffh 3ffh ffh v out(max) = 2.44v ( 2 ) 2 8dah 236h 8dh ~ 0 to 55% range 2.0 ( 3 ) 1 d1dh 347h d1h ~ 0 to 82% range 2 ( 4 ) 68eh 1a3h 68h ~ 0 to 41% range note 1: without the v out pin voltage being clipped. 2: when v bg = 1.22v typical. 3: band gap performance achieves full performance starting from a v dd of 2.0v. 4: it is recommended to use gain = 1 setting instead. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 45 mcp48fvbxx 5.5 latch pin (lat ) the latch pin controls when the volatile dac register value is transferred to the dac wiper. this is useful for applications that need to synchronize the wiper(s) updates to an external event, such as zero crossing or updates to the other wipers on the device. the lat pin is asynchronous to the serial interface operation. when the lat pin is high, transfers from the volatile dac register to the dac wiper are inhibited. the volatile dac register value(s) can still be updated. when the lat pin is low, the volatile dac register value is transferred to the dac wiper. figure 5-8 shows the interaction of the lat pin and the loading of the dac wiper x (from the volatile dac register x). the transfers are level driven. if the lat pin is held low, the corresponding dac wiper is updated as soon as the volatile dac register value is updated. figure 5-8: lat and dac interaction. the lat pin allows the dac wiper to be updated to an external event as well as have multiple dac channels/devices update at a common event. since the dac wiper x is updated from the volatile dac register x, all dacs that are associated with a given lat pin can be updated synchronously. if the application does not require synchronization, then this signal should be tied low. figure 5-9 shows two cases of using the lat pin to control when the wiper register is updated relative to the value of a sine wave signal. figure 5-9: example use of lat pin operation. note: this allows both the volatile dac0 and dac1 registers to be updated while the lat pin is high, and to have outputs synchronously updated as the lat pin is driven low. write command register address vol. dac register x dac wiper x 16 clocks lat sync transfer serial shift reg data (internal signal) lat sync transfer data comment 11 0 no transfer 10 0 no transfer 01 1 vol. dac register x ? dac wiper x 00 0 no transfer case 1: zero crossing of sine wave to update volatile dac0 register (using lat pin) case 2: fixed point crossing of sine wave to update volatile dac0 register (using lat pin) indicates where lat pin pulses active (volatile dac0 register updated). downloaded from: http:/// mcp48fvbxx ds20005466a-page 46 ? 2015 microchip technology inc. 5.6 power-down operation to allow the application to conserve power when the dac operation is not required, three power-down modes are available. the power-down configuration bits (pd1:pd0) control the power-down operation (see figure 5-10 and ta b l e 5 - 5 ). on devices with mul- tiple dacs, each dacs power-down mode is individu- ally controllable. all power-down modes do the following: turn off most of the dac modules internal circuits (output op amp, resistor ladder, et al.) op amp output becomes high-impedance to the v out pin disconnects resistor ladder from reference voltage (v rl ) depending on the selected power-down mode, the following will occur: v out pin is switched to one of two resistive pull-downs (see table 5-5 ): -100k ? (typical) -1k ? (typical) op amp is powered-down and the v out pin becomes high-impedance. there is a delay (t pde ) between the pd1:pd0 bits changing from 00 to either 01 , 10 or 11 with the op amp no longer driving the v out output and the pull-down resistors sinking current. in any of the power-down modes where the v out pin is not externally connected (sinking or sourcing current), the power-down current will typically be ~650 na for a single-dac device. as the number of dacs increases, the devices power-down current will also increase . the power-down bits are modified by using a write command to the volatile power-down register, or a por event which loads the default power-down register values to the volatile power-down register. section 7.0, spi commands describes the spi commands. the write command can be used to update the volatile pd1:pd0 bits. figure 5-10: v out power-down block diagram. table 5-6 shows the current sources for the dac based on the selected source of the dacs reference voltage and if the device is in normal operating mode or one of the power-down modes. note: the spi serial interface circuit is not affected by the power-down mode. this circuit remains active in order to receive any command that might come from the host controller device. table 5-5: power-down bits and output resistive load pd1 pd0 function 00 normal operation 01 1k ? resistor to ground 10 100 k ? resistor to ground 11 open circuit table 5-6: dac current sources device v dd current source pd1:0 = 00 , vref1:0 = pd1:0 ? 00 , vref1:0 = 00 01 10 11 00 01 10 11 output op amp yy y ynn n n resistor ladder yy n ( 1 ) ynn n ( 1 ) n rl op amp n y n y n n n n band gap n y n n n y n n note 1: current is sourced from the v ref pin, not the device v dd . + - gain v out 1 k ? 100 k ? pd1:pd0 v dd pd1:pd0 v w note 1: gain options are 1x and 2x. ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 47 mcp48fvbxx 5.6.1 exiting power-down when the device exits power-down mode, the following occurs: disabled circuits (op amp, resistor ladder, et al.) are turned on the resistor ladder is connected to selected reference voltage (v rl ) the selected pull-down resistor is disconnected the v out output is driven to the voltage represented by the volatile dac registers value and configuration bits the v out output signal will require time as these circuits are powered-up and the output voltage is driven to the specified value as determined by the volatile dac register and configuration bits. a write command forcing the pd1:pd0 bits to 00, will cause the device to exit the power-down mode. 5.7 dac registers, configuration bits, and status bits the mcp48fvbxx devices have volatile memory. table 4-2 shows the volatile memory and its interaction due to a por event. in the volatile memory, there are five configuration bits, the dac registers and two volatile status bits. the volatile dac registers will be either 12 bits (mcp48fvb2x), 10 bits (mcp48fvb1x), or 8 bits (mcp48fvb0x) wide. when the device is first powered-up, it automatically loads the device default values to the volatile memory. the volatile memory determines the analog output (v out ) pin voltage. after the device is powered-up, the user can update the device memory. the memory is read and written using an spi interface. refer to sections 6.0, spi serial interface module and 7.0, spi commands for more details on reading and writing the devices memory. register 4-4 shows the operation of the device status bits, and tab l e 4 - 2 shows the default factory value of the device configuration bits after a por/bor event. there is one status bit (the por bit) which indicates if the device v dd is above or below the por trip point. after a por event, this bit is a 1 . reading the gain control and system status register clears this bit (0). note: since the op amp and resistor ladder were powered-off (0v), the op amps input voltage (v w ) can be considered 0v. there is a delay (t pdd ) between the pd1:pd0 bits updating to 00 and the op amp driving the v out output. the op amps settling time (from 0v) needs to be taken into account to ensure the v out voltage reflects the selected value. downloaded from: http:/// mcp48fvbxx ds20005466a-page 48 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 49 mcp48fvbxx 6.0 spi serial interface module the mcp48fvbxxs spi serial interface module supports the spi serial protocol specification. figure 6-1 shows a typical spi interface connection. the command format and waveforms for the mcp48fvbxx are defined in section 7.0, spi commands . 6.1 overview this section details some of the specific characteristics of the mcp48fvbxxs serial interface module. the following sections discuss some of these device-specific characteristics: communication data rates por/bor interface pins (cs, sck, sdi, sdo, and lat/hvc) 6.2 spi serial interface the mcp48fvbxx devices support the spi serial protocol. this spi operates in slave mode (does not generate the serial clock). the spi interface uses up to four pins. these are: cs - chip select sck - serial clock sdi - serial data in sdo - serial data out a typical spi interface is shown in figure 6-1 . in the spi interface, the masters output pin is connected to the slaves input pin, and the masters input pin is connected to the slaves output pin. the mcp48fvbxx spi module supports two (of the four) standard spi modes. these are mode 0 , 0 and 1 , 1 . the spi mode is determined by the state of the sck pin (v ih or v il ) when the cs pin transitions from inactive (v ih ) to active (v il ). an additional hvc pin is available for high voltage command support (for compatibility with mcp48febxx devices). the hvc pin is high-voltage tolerant. 6.3 communication data rates the mcp48fvbxx devices support clock rates (bit rate) of up to 20 mhz for write commands and 10 mhz for read commands. for most applications, the write time will be considered more important, since that is how the device operation is controlled. 6.4 por/bor on a por/bor event, the spi serial interface module state machine is reset, which includes that the devices memory address pointer is forced to 00h. figure 6-1: typical spi interface block diagram. sdi sdo mcp48fvbxx sdo sdi sck sck (master out - slave in (mosi)) (master in - slave out (miso)) host controller typical spi interface connections cs i/o note 1: the pin is compatible with hvc levels used for non-volatile mcp48febxx devices. hvc i/o ( 1 ) downloaded from: http:/// mcp48fvbxx ds20005466a-page 50 ? 2015 microchip technology inc. 6.5 interface pins (cs , sck, sdi, sdo, and lat /hvc) the operation of the five interface pins is discussed in this section. these pins are: sdi (serial data in) sdo (serial data out) sck (serial clock) cs (chip select) lat /hvc ( high voltage command) the serial interface works on a 24-bit boundary. the chip select (cs ) pin frames the spi commands. 6.5.1 serial data in (sdi) the serial data in (sdi) signal is the data signal into the device. the value on this pin is latched on the rising edge of the sck signal. 6.5.2 serial data out (sdo) the serial data out (sdo) signal is the data signal out of the device. the value on this pin is driven on the falling edge of the sck signal. once the cs pin is forced to the active level (v il ), the sdo pin will be driven. the state of the sdo pin is determined by the serial bits position in the command, the command selected, and if there is a command error state (cmderr). 6.5.3 serial clock (sck) (spi frequency of operation) the spi interface is specified to operate up to 20 mhz. the actual clock rate depends on the configuration of the system and the serial command used. table 6-1 shows the sck frequency for different configurations. table 6-1: sck frequency 6.5.4 the cs signal the chip select (cs ) signal is used to select the device and frame a command sequence. to start a command, or sequence of commands, the cs signal must transition from the inactive state (v ih ) to the active state (v il ). after the cs signal has gone active, the sdo pin is driven and the clock bit counter is reset. if an error condition occurs for an spi command, then the command bytes command error (cmderr) bit (on the sdo pin) will be driven low (v il ). to exit the error condition, the user must take the cs pin to the v ih level. when the cs pin returns to the inactive state (v ih ), the spi module resets (including the address pointer). while the cs pin is in the inactive state (v ih ), the serial interface is ignored. this allows the host controller to interface to other spi devices using the same sdi, sdo, and sck signals. 6.5.5 the hvc signal the hvc pin is compatible with high voltage com- mands levels (used with mcp48febxx devices). 6.6 the spi modes the spi module supports two (of the four) standard spi modes. these are mode 0 , 0 and 1 , 1 . the spi mode is determined by the state of the sck pin (v ih or v il ) when the cs pin transitions from inactive (v ih ) to active (v il ). 6.6.1 mode 0,0 in mode 0,0: sck idle state = low (v il ) data is clocked in on the sdi pin on the rising edge of sck data is clocked out on the sdo pin on the falling edge of sck 6.6.2 mode 1,1 in mode 1,1: sck idle state = high (v ih ) data is clocked in on the sdi pin on the rising edge of sck data is clocked out on the sdo pin on the falling edge of sck memory type access command read write volatile memory sdi, sdo 10 mhz 20 mhz ( 1 ) note 1: write interface speed is faster than read interface speed due to read access times. note: there is a required delay after the cs pin goes active to the 1st edge of the sck pin. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 51 mcp48fvbxx 7.0 spi commands this section documents the commands that the device supports. the mcp48fvbxxs spi command format supports 32 memory address locations and two commands. the two commands are: write command (c1:c0 = 00 ) read command (c1:c0 = 11 ) the supported commands are shown in table 7-1 . these commands allow for both single data or continuous data operation. tab le 7 - 1 also shows the required number of bit clocks for each commands different mode of operation. the 24-bit commands (see figure 7-1 ) are used to read and write to the device registers ( read command and write command ). these commands contain a command byte and two data bytes. table 7-2 shows an overview of all the spi commands and their interaction with other device features. table 7-1: spi commands - number of clocks command # of bit clocks ( 1 ) data update rate (8-bit/10-bit/12-bit) (data words/second) comments operation code hv mode c1 c0 @ 1mhz @ 10 mhz @ 20 mhz write command 00 no ( 2 ) single 24 41,666 416,666 833,333 00 no ( 2 ) continuous 24 ? n 41,666 416,666 833,333 for 10 data words read command 11 no ( 2 ) single 24 41,666 416,666 n.a. 11 no ( 2 ) continuous 24 ? n 41,666 416,666 n.a. for 10 data words note 1: n indicates the number of times the command operation is to be repeated. 2: if the state of the hvc pin is v ihh , then the command is ignored, but a command error condition (cmderr) will not be generated. downloaded from: http:/// mcp48fvbxx ds20005466a-page 52 ? 2015 microchip technology inc. 7.0.1 command byte the command byte has three fields: the address, the command, and one data bit (see figure 7-1 ). the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location getting accessed is contained in the command bytes ad4:ad0 bits. the action desired is contained in the command bytes c1:c0 bits, see tab le 7 -3 . c1:c0 determines if the desired memory location will be read or written. as the command byte is being loaded into the device (on the sdi pin), the devices sdo pin is driving. the sdo pin will output high bits for the first seven bits of that command. on the 8th bit, the sdo pin will output the cmderr bit state (see section 7.0.3, error condition ). 7.0.2 data bytes these commands concatenate the two data bytes after the command byte, for a 24-bit long command (see figure 7-1 ). figure 7-1: 24-bit spi command format. table 7-2: command bits overview c1:c0 bit states command # of bits normal or hv 00 write data 24 bits normal 01 reserved 10 reserved 11 read data 24 bits normal a d 4 a d 3 a d 2 a d 1 a d 0 c 1 c 0 c m d e rr d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 memory 24-bit command data bits (8, 10, or 12 bits) address command bits 0 0 = write data 0 1 = reserved 1 0 = reserved 1 1 = read data c c 1 0 command bits command byte data word (2 bytes) ( 1 ) note 1: this command uses the 24-bit format. ( 1 ) downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 53 mcp48fvbxx 7.0.3 error condition the command error (cmderr) bit indicates if the five address bits received (ad4:ad0) and the two command bits received (c1:c0) are a valid combination (see figure 7-1 ). the cmderr bit is high if the combination is valid and low if the combination is invalid. spi commands that do not have a multiple of eight clocks are ignored. once an error condition has occurred, any following commands are ignored. all following sdo bits will be low until the cmderr condition is cleared by forcing the cs pin to the inactive state (v ih ). 7.0.3.1 aborting a transmission all spi transmissions must have the correct number of sck pulses to be executed. the command is not executed until the complete number of clocks has been received. if the cs pin is forced to the inactive state (v ih ), the serial interface is reset. partial com- mands are not executed. spi is more susceptible to noise than other bus protocols. the most likely case is that noise corrupts the value of the data being clocked into the mcp48fvbxx or the sck pin is injected with extra clock pulses. this may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. the extra sck pulse will also cause the spi data (sdi) and clock (sck) to be out of sync. forcing the cs pin to the inactive state (v ih ) resets the serial interface. the mcp48fvbxxs spi interface will ignore activity on the sdi and sck pins until the cs pin transition to the active state is detected (v ih to v il ). 7.0.4 continuous commands the device supports the ability to execute commands continuously. while the cs pin is in the active state (v il ), any sequence of valid commands may be received. the following example is a valid sequence of events: 1. cs pin driven active (v il ) 2. read command 3. write command (volatile memory) 4. cs pin driven inactive (v ih ) note 1: when data is not being received by the mcp48fvbxx, it is recommended that the cs pin be forced to the inactive level (v ih ). 2: it is also recommended that long continuous command strings be broken down into single commands or shorter continuous command strings. this reduces the probability of noise on the sck pin corrupting the desired spi commands. note 1: it is recommended that while the cs pin is active, only one type of command should be issued. when changing commands, it is advisable to take the cs pin inactive then force it back to the active state. 2: it is also recommended that long command strings should be broken down into shorter command strings. this reduces the probability of noise on the sck pin, corrupting the desired spi command string. downloaded from: http:/// mcp48fvbxx ds20005466a-page 54 ? 2015 microchip technology inc. 7.1 write command write commands are used to transfer data to the desired memory location (from the host controller). write commands can be structured as either single or continuous. the format of the command is shown in figures 7-2 (single) and 7-3 (continuous). a write command to a volatile memory location changes that location after a properly formatted write command has been received. 7.1.1 single write to volatile memory the write operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 24-bit write command (command byte and data bytes) is then clocked in on the sck and sdi pins. once all 24 bits have been received, the specified volatile address is updated. a write will not occur if the write command is not exactly 24 clock pulses. this protects against system issues corrupting the volatile memory locations. figures 7-4 and 7-5 show the waveforms for a single write (depending on spi mode). 7.1.2 continuous writes to volatile memory a continuous write mode of operation is possible when writing to the devices volatile memory registers (see table 7-3 ). figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. figure 7-2: write command - sdi and sdo states. note 1: during device communication, if the device address/command combination is invalid or an unimplemented device address is specified, then the mcp48fvbxx will generate a command error state. to reset the spi state machine, the cs pin must transition to the inactive state (v ih ). table 7-3: volatile memory addresses address single-channel dual-channel 00h yes yes 01h no yes 08h yes yes 09h yes yes 0ah yes yes a d 4 a d 3 a d 2 a d 1 a d 0 00c m d e rr d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 111111111111111111111111valid ( 1 ) 1111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) address data bits (8, 10, or 12 bits) sdi sdo command note 1: if a valid address/command occurs, then the data bits are dependent on the resolution of the device. 12-bit = d11:d00, 10-bit = d09:d00, and 8-bit = d07:d00. data is right justified for ease of hos t controller operation (i.e., no data manipulation before transmitting the desired value). 2: unimplemented data bits (d15:d12 on 12-bit device, d15:d10 on 10-bit device, d15:d08 on 8-bit device) will be output as 1 . 3: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 55 mcp48fvbxx figure 7-3: continuous write sequence. a d 4 a d 3 a d 2 a d 1 a d 0 00c m d e rr d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 111111111111111111111111valid ( 1 ) 0 0 0 0 0 0 0 ( 4 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo a d 4 a d 3 a d 2 a d 1 a d 0 00c m d e rr d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 111111111111111111111111valid ( 1 ) 0 0 0 0 0 0 0 ( 4 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo a d 4 a d 3 a d 2 a d 1 a d 0 00c m d e rr d 15 d 14 d 13 d 12 d 11 d 10 d 09 d 08 d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 111111111111111111111111valid ( 1 ) 1111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo address data bits (8, 10, or 12 bits) command note 1: if a valid address/command occurs, then the data bits are dependent on the resolution of the device. 12-bit = d11:d00, 10-bit = d09:d00, and 8-bit = d07:d00. data is right justified for ease of host control ler operation (i.e., no data manipulation before transmitting the desired value). 2: unimplemented data bits (d15:d12 on 12-bit device, d15:d10 on 10-bit device, d15:d08 on 8-bit device) will be output as 1 . 3: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). 4: this cmderr bit will be forced to 0 , regardless if this address+command combination is valid. this command will not be completed and requires the cs pin to return to v ih to clear the cmderr condition. address data bits (8, 10, or 12 bits) command address data bits (8, 10, or 12 bits) command downloaded from: http:/// mcp48fvbxx ds20005466a-page 56 ? 2015 microchip technology inc. figure 7-4: 24-bit write command (c1:c0 = ? 00 ?) - spi waveform with pic mcu (mode 1,1). figure 7-5: 24-bit write command (c1:c0 = ?00?) - spi waveform with pic mcu (mode 0,0). hvc ( 1 ) cs sck pic write to sspbuf sdi input sample sdo bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit1 bit0 bit23 bit22 bit21 bit20 0 bit16 bit15 bit1 bit0 ad4 ad3 ad2 ad1 bit19 0 d16 d15 d1 d0 v ih v il cmderr bit ad0 note 1: if the state of the hvc pin is v ihh , then the command is ignored, but a command error condition (cmderr) will not be generated. hvc ( 1 ) cs sck pic write to sspbuf sdi input sample sdo bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit1 bit0 bit23 bit22 bit21 bit20 bit16 bit15 bit1 bit0 ad4 ad3 ad2 ad1 0 d16 d15 d1 d0 v ih v il cmderr bit 0 bit19 ad0 note 1: if the state of the hvc pin is v ihh , then the command is ignored, but a command error condition (cmderr) will not b e generated. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 57 mcp48fvbxx 7.2 read command the read command is a 24-bit command and is used to transfer data from the specified memory location to the host controller. the read command can be issued to the volatile memory locations. the format of the command as well as an example sdi and sdo data is shown in figure 7-6 . the first 7-bits of the read command determine the address and the command. the 8th clock will output the cmderr bit on the sdo pin. by means of the remaining 16 clocks, the device will transmit the data bits of the specified address (ad4:ad0). the read command formats include: single read continuous reads 7.2.1 lat pin interaction during a read command of the dacx registers, if the lat pin transitions from v ih to v il , then the read data may be corrupted. this is due to the fact that the data being read is the output value and not the dac register value. the lat pin transition causes an update of the output value. based on the dac output value, the dacx register value, and the command bit where the lat pin transitions, the value being read could be corrupted. if lat pin transitions occur during a read of the dacx register, it is recommended that sequential reads be performed until the two most recent read values match. then the most recent read data is good. 7.2.2 single read the read command operation requires that the cs pin be in the active state (v il ). typically, the cs pin will be in the inactive state (v ih ) and is driven to the active state (v il ). the 24-bit read command (command byte and data byte) is then clocked in on the sck and sdi pins. the sdo pin starts driving data on the 8th bit (cmderr bit), and the addressed data comes out on the 9th through 24th clocks. figure 7-6: read command - sdi and sdo states. note 1: during device communication, if the device address/command combination is invalid or an unimplemented address is specified, then the mcp48fvbxx will command error that byte. to reset the spi state machine, the cs pin must be driven to the v ih state. 2: if the lat pin is high (v ih ), reads of the volatile dac register address returns that dacs output value, not the internal register. 3: read commands ignore any high volt- age command levels that are present on the hvc pin. a d 4 a d 3 a d 2 a d 1 a d 0 11c m d e rr x x x x x x x xxxxxxxxx 11111111 1 1 1 1 d d d dddddddddvalid ( 1 ) 1111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdisdo note 1: if a valid address/command occurs, then the data bits are dependent on the resolution of the device. 12-bit = d11:d00, 10-bit = d09:d00, and 8-bit = d07:d00. data is right justified for ease of host control ler operation (i.e., no data manipulation before transmitting the desired value). 2: unimplemented data bits (d15:d12 on 12-bit device, d15:d10 on 10-bit device, d15:d08 on 8-bit device) will be output as 1 . 3: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). address data bits (8, 10, or 12 bits) command downloaded from: http:/// mcp48fvbxx ds20005466a-page 58 ? 2015 microchip technology inc. 7.2.3 continuous reads continuous-reads format allows the devices memory to be read quickly. continuous reads are possible to all memory locations. figure 7-7 shows the sequence for three continuous reads. the reads do not need to be to the same memory address. figure 7-7: continuous-reads sequence. a d 4 a d 3 a d 2 a d 1 a d 0 11c m d e rr x x x x x x x xxxxxxxxx 111111111111111111111111valid ( 1 ) 0 0 0 0 0 0 0 ( 4 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo a d 4 a d 3 a d 2 a d 1 a d 0 11c m d e rr x x x x x x x xxxxxxxxx 111111111111111111111111valid ( 1 ) 0 0 0 0 0 0 0 ( 4 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo a d 4 a d 3 a d 2 a d 1 a d 0 11c m d e rr x x x x x x x xxxxxxxxx 111111111111111111111111valid ( 1 ) 1111111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0invalid ( 2 , 3 ) sdi sdo address data bits (8, 10, or 12 bits) command address data bits (8, 10, or 12 bits) command address data bits (8, 10, or 12 bits) command note 1: if a valid address/command occurs, then the data bits are dependent on the resolution of the device. 12-bit = d11:d00, 10-bit = d09:d00, and 8-bit = d07:d00. data is right justified for ease of host controll er operation (i.e., no data manipulation before transmitting the desired value). 2: unimplemented data bits (d15:d12 on 12-bit device, d15:d10 on 10-bit device, d15:d08 on 8-bit device) will be output as 1 . 3: if an error condition occurs (cmderr = l), all following sdo bits will be low until the cmderr condition is cleared (the cs pin is forced to the inactive state). 4: this cmderr bit will be forced to 0 , regardless if this address+command combination is valid. this command will not be completed and requires the cs pin to return to v ih to clear the cmderr condition. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 59 mcp48fvbxx figure 7-8: 24-bit read command (c1:c0 = ? 11 ?) - spi waveform with pic mcu (mode 1,1). figure 7-9: 24-bit read command (c1:c0 = ? 11 ?) - spi waveform with pic mcu (mode 0,0). hvc ( 1 ) cs sck pic write to sspbuf sdi input sample sdo bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit1 bit0 bit23 bit22 bit21 bit20 1 bit16 bit15 bit1 bit0 ad4 ad3 ad2 ad1 bit19 1 d16 d15 d1 d0 v ih v il cmderr bit ad0 note 1: if the state of the hvc pin is vihh, then the command is ignored, but a command error condition ( cmderr) will not be generated. hvc ( 1 ) cs sck pic write to sspbuf sdi input sample sdo bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit1 bit0 bit23 bit22 bit21 bit20 bit16 bit15 bit1 bit0 ad4 ad3 ad2 ad1 1 d16 d15 d1 d0 v ih v il cmderr bit 1 bit19 ad0 note 1: if the state of the hvc pin is v ihh , then the command is ignored, but a command error condition (cmderr) will not b e generated. downloaded from: http:/// mcp48fvbxx ds20005466a-page 60 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 61 mcp48fvbxx 8.0 typical applications the mcp48fvbxx devices are general purpose, single/dual-channel voltage output dacs for various applications where a precision operation with low power and volatile memory is needed. applications generally suited for the devices are: set point or offset trimming sensor calibration portable instrumentation (battery-powered) motor control 8.1 power supply considerations the power source should be as clean as possible. the power supply to the device is also used for the dac voltage reference internally if the internal v dd is selected as the resistor ladders reference voltage (vrxb:vrxa = 00). any noise induced on the v dd line can affect the dac performance. typical applications will require a bypass capacitor in order to filter out high-frequency noise on the v dd line. the noise can be induced onto the power supplys traces or as a result of changes on the dac output. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-1 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) in parallel on the v dd line. these capacitors should be placed as close to the v dd pin as possible (within 4 mm). if the application circuit has separate digital and analog power supplies, the v dd and v ss pins of the device should reside on the analog plane. figure 8-1: bypass filtering example circuit. analog v dd 23 4 97 cs sck sdo v ss v out0 8 to m c u c 1 : 0.1 f capacitor ceramic c 2 : 10 f capacitor tantalum c 3 : ~ 0.1 f optional to reduce noise in v out pin c 4 : 0.1 f capacitor ceramic c 5 : 10 f capacitor tantalum c 6 : 0.1 f capacitor ceramic c 2 c 1 mcp48fvbx2 optional (a) circuit when v dd is selected as reference ( note: v dd is connected to the reference circuit internally.) (b) circuit when external reference is used. output v ref 5 6 lat /hvc v out1 c 4 c 3 analog v dd 23 4 97 cs sck sdo v ss v out0 8 to m c u c 2 c 1 mcp48fvbx2 optional output v ref 5 6 lat /hvc v out1 c 5 optional v ref c 6 c 4 c 3 1 10 v dd sdi 1 10 v dd sdi downloaded from: http:/// mcp48fvbxx ds20005466a-page 62 ? 2015 microchip technology inc. 8.2 application examples the mcp48fvbxx devices are rail-to-rail output dacs designed to operate with a v dd range of 2.7v to 5.5v. the internal output operational amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. the user can use gain of 1 or 2 of the output operational amplifier by setting the configuration register bits. also, the user can use internal v dd as the reference or use an external reference. various user options and easy-to-use features make the devices suitable for various modern dac applications. application examples include: decreasing output step size building a window dac bipolar operation selectable gain and offset bipolar voltage output designing a double-precision dac building programmable current source serial interface communication times power supply considerations layout considerations 8.2.1 dc set point or calibration a common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. for example, the mcp48fvb2x provides 4096 output steps. if voltage reference is 4.096v (where gx = 0 ), the lsb size is 1 mv. if a smaller output step size is desired, a lower external voltage reference is needed. 8.2.1.1 decreasing output step size if the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8v may be desired with about 200 v resolution per step. two common methods to achieve small step size are: using lower v ref pin voltage: using an external voltage reference (v ref ) is an option if the external reference is available with the desired output voltage range. however, occasionally, when using a low-voltage reference voltage, the noise floor causes a snr error that is intolerable. using a voltage divider on the dacs output: using a voltage divider provides some advantages when external voltage reference needs to be very low or when the desired output voltage is not available. in this case, a larger value reference voltage is used while two resistors scale the output range down to the precise desired level. figure 8-2 illustrates this concept. a bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. figure 8-2: example circuit of set-point or threshold calibration. equation 8-1: v out and v trip calculations r 1 v cc + v cc C v out spi 4-wire v ref optional mcp48fvbxx v dd v o r 2 c 1 r sense comp. v dd v trip + - v trip v out r 2 r 1 r 2 + -------------------- ?? ?? ?? = v out = v ref g dac register value 2 n downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 63 mcp48fvbxx 8.2.1.2 building a window dac when calibrating a set point or threshold of a sensor, typically only a small portion of the dac output range is utilized. if the lsb size is adequate enough to meet the applications accuracy needs, the unused range is sacrificed without consequences. if greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. if the threshold is not near v ref , 2 ? v ref , or v ss , then creating a window around the threshold has several advantages. one simple method to create this window is to use a voltage divider network with a pull-up and pull-down resistor. figures 8-3 and 8-5 illustrate this concept. figure 8-3: single-supply ?window? dac. equation 8-2: v out and v trip calculations 8.3 bipolar operation bipolar operation is achievable by utilizing an external operational amplifier. this configuration is desirable due to the wide variety and availability of op amps. this allows a general purpose dac, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. figure 8-4 illustrates a simple bipolar voltage source configuration. r 1 and r 2 allow the gain to be selected, while r 3 and r 4 shift the dac's output to a selected offset. note that r4 can be tied to v dd instead of v ss if a higher offset is desired. figure 8-4: digitally-controlled bipolar voltage source example circuit. equation 8-3: v out , v oa+ , and v o calculations r 1 v cc + v cc C v o spi 4-wire v ref optional mcp48fvbxx v dd v out r 2 c 1 r 3 v cc + v cc C r sense comp. v trip + - r 23 r 2 r 3 r 2 r 3 + ------------------- = v 23 v cc+ r 2 ?? v cc- r 3 ?? + r 2 r 3 + ------------------------------------------------------ = v trip v out r 23 v 23 r 1 + r 1 r 23 + -------------------------------------------- - = thevenin equivalent r 1 r 23 v 23 v out v trip v out = v ref g dac register value 2 n r 3 v cc + v cc C v o spi 4-wire v ref optional mcp48fvbxx v dd r 2 v out v in r 1 r 4 c 1 v oa+ v oa+ = v out r 4 r 3 + r 4 v out = v ref g dac register value 2 n v o = v oa+ (1 + ) - v dd ( ) r 2 r 1 r 2 r 1 downloaded from: http:/// mcp48fvbxx ds20005466a-page 64 ? 2015 microchip technology inc. 8.4 selectable gain and offset bipolar voltage output in some applications, precision digital control of the output range is desirable. figure 8-5 illustrates how to use dac devices to achieve this in a bipolar or single-supply application. this circuit is typically used for linearizing a sensor whose slope and offset varies. the equation to design a bipolar window dac would be utilized if r 3 , r 4 and r 5 are populated. bipolar dac example an output step size of 1 mv with an output range of 2.05v is desired for a particular application. the equation can be simplified to: equation 8-4: equation 8-5: figure 8-5: bipolar voltage source with selectable gain and offset. equation 8-6: v out , v oa+ , and v o calculations equation 8-7: bipolar window dac using r 4 and r 5 step 1: calculate the range: +2.05v C (-2.05v) = 4.1v. step 2: calculate the resolution needed: 4.1v/1 mv = 4100 since 2 12 = 4096, 12-bit resolution is desired. step 3: the amplifier gain (r 2 /r 1 ), multiplied by full-scale v out (4.096v), must be equal to the desired minimum output to achieve bipolar operation. since any gain can be realized by choosing resistor values (r 1 +r 2 ), the v ref value must be selected first. if a v ref of 4.096v is used, solve for the amplifiers gain by setting the dac to 0, knowing that the output needs to be -2.05v. step 4: next, solve for r 3 and r 4 by setting the dac to 4096, knowing that the output needs to be +2.05v. r 2 ? r 1 -------- - 2.05 ? 4.096v ---------------- - = if r 1 = 20 k ? and r 2 = 10 k ? , the gain will be 0.5. r 2 r 1 ----- - 12 -- -= r 4 r 3 r 4 + ?? ----------------------- - 2.05v 0.5 4.096v ? ?? + 1.5 4.096v ? ------------------------------------------------------- 23 -- - == if r 4 = 20 k ? , then r 3 = 10 k ? r 3 v cc + v cc C v out spi 4-wire v ref optional mcp48fvbxx v dd r 2 v o v in r 1 r 4 c 1 r 5 optional v oa+ v cc + v cc C c 1 = 0.1 f offset adjust gain adjust v out = v ref g dac register value 2 n v oa+ = v out r 4 + v cc- r 5 r 3 + r 4 v o = v oa+ ( 1 + ) - v in ( ) r 2 r 1 r 2 r 1 thevenin equivalent v 45 v cc+ r 4 v cc- r 5 + r 4 r 5 + -------------------------------------------- - = v in+ v out r 45 v 45 r 3 + r 3 r 45 + -------------------------------------------- - = r 45 r 4 r 5 r 4 r 5 + ------------------- = v o v in+ 1 r 2 r 1 ----- - + ?? ?? v a r 2 r 1 ----- - ?? ?? ? = offset adjust gain adjust downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 65 mcp48fvbxx 8.5 designing a double-precision dac figure 8-6 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. this requires two 12-bit dacs. this design is simply a voltage divider with a buffered output. double-precision dac example if a similar application to the one developed in bipolar dac example required a resolution of 1 v instead of 1 mv and a range of 0v to 4.1v, then 12-bit resolution would not be adequate. figure 8-6: simple double-precision dac using mcp48fvbx2. equation 8-8: v out calculation 8.6 building programmable current source figure 8-7 shows an example of building a programmable current source using a voltage follower. the current sensor resistor is used to convert the dac voltage output into a digitally-selectable current source. the smaller r sense is, the less power dissipated across it. however, this also reduces the resolution that the current can be controlled. figure 8-7: digitally-controlled current source. step 1: calculate the resolution needed: 4.1v/1 v = 4.1 x 10 6 . since 2 22 =4.2x10 6 , 22-bit resolution is desired. since dnl = 1.0 lsb, this design can be attempted with the 12-bit dac. step 2: since dac1s v out1 has a resolution of 1 mv, its output only needs to be pulled 1/1000 to meet the 1 v target. dividing v out0 by 1000 would allow the application to compensate for dac1s dnl error. step 3: if r 2 is 100 ? , then r 1 needs to be 100 k ? . step 4: the resulting transfer function is shown in equation 8-8 . r 1 v cc + v cc C v out spi 4-wire v ref optional mcp48fvbx2 v dd spi 4-wire v ref optional mcp48fvbx2 v dd r 2 0.1 f v out0 v out1 (dac0) (dac1) v out = gx = selected op amp gain v out0 r 2 + v out1 r 1 r 1 + r 2 v out0 = (v ref g dac0 register value)/4096 v out1 = (v ref g dac1 register value)/4096 where: r sense i b load i l v cc + v cc C v out i b i l ? ---- = ??? ? common-emitter current gain ? where v dd spi 4-wire v ref optional mcp48fvbxx v dd (or v ref ) i l v out r sense ------------------ ? ? 1+ ------------ - ? = downloaded from: http:/// mcp48fvbxx ds20005466a-page 66 ? 2015 microchip technology inc. 8.7 serial interface communication times table 8-1 shows time/frequency of the supported operations of the spi serial interface for the different serial interface operational frequencies. this, along with the v out output performance (such as slew rate), would be used to determine your applications volatile dac register update rate. table 8-1: serial interface times / frequencies command # of bit clocks ( 1 ) data update rate (8-bit/10-bit/12-bit) (data words/second) comments operation code mode c 1 c 0 1 mhz 10 mhz 20 mhz ( 2 ) write command 0 0 single 24 41,666 416,666 833,333 0 0 continuous 24 ??? n 41,666 416,666 833,333 for 10 data words read command 1 1 single 24 41,666 416,666 n.a. 1 1 continuous 24 ??? n 41,666 416,666 n.a. for 10 data words note 1: n indicates the number of times the command operation is to be repeated. 2: write command only. downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 67 mcp48fvbxx 8.8 design considerations in the design of a system with the mcp48fvbxx devices, the following considerations should be taken into account: power supply considerations layout considerations 8.8.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of noise sources on signal integrity. figure 8-8 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-8: typical microcontroller connections. 8.8.2 layout considerations several layout considerations may be applicable to your application. these may include: noise pcb area requirements 8.8.2.1 noise inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp48fvbxxs performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. separate digital and analog ground planes are recommended. in this case, the v ss pin and the ground pins of the v dd capacitors should be terminated to the analog ground plane. 8.8.2.2 pcb area requirements in some applications, pcb area is a criteria for device selection. tab l e 8 - 2 shows the typical package dimensions and area for the 10-lead msop package. v dd v dd v ss v ss mcp48fvbxx 0.1 f pic ? microcontroller 0.1 f sdi v out v ref sdo sck cs note: breadboards and wire-wrapped boards are not recommended. table 8-2: package footprint ( 1 ) package package footprint pins type code dimensions (mm) area (mm 2 ) length width 10 msop un 3.00 4.90 14.70 note 1: does not include recommended land pattern dimensions. dimensions are typical values. downloaded from: http:/// mcp48fvbxx ds20005466a-page 68 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 69 mcp48fvbxx 9.0 development support development support can be classified into two groups. these are: development tools technical documentation 9.1 development tools the mcp48fvbxx devices currently do not have any development tools or bond-out boards. please visit the device's web product page (development tools tab) for the development tools availability after the release of this data sheet. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta b l e 9 - 1 lists some of these documents. table 9-1: technical documentation application note number title literature # an1326 using the mcp4728 12-bit dac for ldmos amplifier bias control applications ds01326 signal chain design guide ds21825 analog solutions for automotive applications design guide ds01005 downloaded from: http:/// mcp48fvbxx ds20005466a-page 70 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 71 mcp48fvbxx 10.0 packaging information 10.1 package marking information device number code device number code MCP48FVB01-e/un 48fv01 mcp48fvb02-e/un 48fv02 MCP48FVB01t-e/un 48fv01 mcp48fvb02t-e/un 48fv02 mcp48fvb11-e/un 48fv11 mcp48fvb12-e/un 48fv12 mcp48fvb11t-e/un 48fv11 mcp48fvb12t-e/un 48fv12 mcp48fvb21-e/un 48fv21 mcp48fvb22-e/un 48fv22 mcp48fvb21t-e/un 48fv21 mcp48fvb22t-e/un 48fv22 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 10-lead msop example 48fv01 548256 3 e 3 e downloaded from: http:/// mcp48fvbxx ds20005466a-page 72 ? 2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 73 mcp48fvbxx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un downloaded from: http:/// mcp48fvbxx ds20005466a-page 74 ? 2015 microchip technology inc. 10-lead plastic micro small otline package (un) [msop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 75 mcp48fvbxx appendix a: revision history revision a (december 2015) original release of this document. downloaded from: http:/// mcp48fvbxx ds20005466a-page 76 ? 2015 microchip technology inc. appendix b: terminology b.1 resolution resolution is the number of dac output states that divide the full-scale range. for the 12-bit dac, the resolution is 2 12 , meaning the dac code ranges from 0 to 4095. b.2 least significant bit (lsb) this is the voltage difference between two successive codes. for a given output voltage range, it is divided by the resolution of the device ( equation b-1 ). the range may be v dd (or v ref ) to v ss (ideal), the dac register codes across the linear range of the output driver (measured 1), or full-scale to zero-scale (measured 2). equation b-1: lsb voltage calculation b.3 monotonic operation monotonic operation means that the devices output voltage (v out ) increases with every 1 code step (lsb) increment (from v ss to the dacs reference voltage (v dd or v ref )). figure b-1: v w (v out ). note: when there are 2 n resistors in the resistor ladder and 2 n tap points, the full-scale dac register code is the resistor element (1 lsb) from the source reference voltage (v dd or v ref ). v lsb(measured) = v out(@4000) - v out(@100) (4000 - 100) ideal v lsb(ideal) = or v dd 2 n v ref 2 n measured 1 v lsb = v out(@fs) - v out(@zs) 2 n - 1 measured 2 2 n = 4096 (mcp48fxb2x) = 1024 (mcp48fxb1x) = 256 (mcp48fxb0x) 40h3fh 3eh 03h 02h 01h 00h wiper code voltage (v w ~= v out ) v w (@ tap) v s0 v s1 v s3 v s63 v s64 v w = v sn + v zs(@ tap 0) n = 0 n = ? downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 77 mcp48fvbxx b.4 full-scale error (e fs ) the full-scale error (see figure b-3 ) is the error on the v out pin relative to the expected v out voltage (theoretical) for the maximum device dac register code (code fffh for 12-bit, code 3ffh for 10-bit, and code ffh for 8-bit) (see equation b-2 ). the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v ss ) greater than specified, the full-scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-2: full-scale error b.5 zero-scale error (e zs ) the zero-scale error (see figure b-2 ) is the difference between the ideal and the measured v out voltage with the dac register code equal to 000h ( equation b-3 ). the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v dd ) greater than specified, the zero-scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-3: zero-scale error b.6 total unadjusted error (e t ) the total unadjusted error (e t ) is the difference between the ideal and measured v out voltage. typically, calibration of the output voltage is implemented to improve system performance. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation b-4 shows the total unadjusted error calculation. equation b-4: total unadjusted error calculation e fs = v out(@fs) - v ideal(@fs) v lsb(ideal) where: e fs is expressed in lsb. v out(@fs) = the v out voltage when the dac register code is at full-scale. v ideal(@fs) = the ideal output voltage when the dac register code is at full-scale. v lsb(ideal) = the theoretical voltage step size. e zs = v out(@zs) v lsb(ideal) where: e zs is expressed in lsb. v out(@zs) =the v out voltage when the dac register code is at zero-scale. v lsb(ideal) = the theoretical voltage step size. where: e t is expressed in lsb. v out_actual(@code) = the measured dac output voltage at the specified code. v out_ideal(@code) = the calculated dac output voltage at the specified code. ( code * v lsb(ideal) ) v lsb(ideal) =v ref /# steps 12-bit = v ref /4096 10-bit = v ref /1024 8-bit = v ref / 256 e t = ( v out_actual(@code) - v out_ideal(@code) ) v lsb(ideal) downloaded from: http:/// mcp48fvbxx ds20005466a-page 78 ? 2015 microchip technology inc. b.7 offset error (e os ) the offset error is the delta voltage of the v out voltage from the ideal output voltage at the specified code. this code is specified where the output amplifier is in the linear operating range; for the mcp48fvbxx we specify code 100 (decimal). offset error does not include gain error. figure b-2 illustrates this. this error is expressed in mv. offset error can be neg- ative or positive. the offset error can be calibrated by software in application circuits. figure b-2: offset error and zero-scale error. b.8 offset error drift (e osd ) offset error drift is the variation in offset error due to a change in ambient temperature. offset error drift is typically expressed in ppm/ o c or v/ o c. b.9 gain error (e g ) gain error is a calculation based on the ideal slope using the voltage boundaries for the linear range of the output driver (ex code 100 and code 4000) (see figure b-3 ). the gain error calculation nullifies the devices offset error. gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. gain error is usually expressed as percent of full-scale range (% of fsr) or in lsb. fsr is the ideal full-scale voltage of the dac (see equation b-5 ). figure b-3: gain error and full-scale error example. equation b-5: example gain error b.10 gain-error drift (e gd ) gain-error drift is the variation in gain error due to a change in ambient temperature. gain error drift is typically expressed in ppm/ o c (of full-scale range). ideal transfer actual dac input code 0 zero-scale error (e zs ) offset function 100 4000 v out error (e os ) transfer function v out ideal transfer actual dac input code 0 full-scale error (e fs ) gain error (e g ) function 100 4000 4095 v ref transfer function (@ code = 4000) ideal transfer function shifted by offset error (crosses at start of defined linear range) where: e g is expressed in % of full-scale range (fsr). v out(@4000) = the measured dac output voltage at the specified code. v out_ideal(@4000) = the calculated dac output voltage at the specified code. ( 4000 * v lsb(ideal) ) v os = measured offset voltage. v full scale range = expected full-scale output value (such as the v ref voltage). e g = 100 ( v out(@4000) - v os - v out_ideal(@4000) ) v full-scale range downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 79 mcp48fvbxx b.11 integral nonlinearity (inl) the integral nonlinearity (inl) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line) passing through the defined end points of the dac transfer function (after offset and gain errors have been removed). in the mcp48fvbxx, inl is calculated using the defined end points, dac code 100 and code 4000. inl can be expressed as a percentage of full-scale range (fsr) or in lsb. inl is also called relative accuracy. equation b-6 shows how to calculate the inl error in lsb and figure b-4 shows an example of inl accuracy. positive inl means higher v out voltage than ideal. negative inl means lower v out voltage than ideal. equation b-6: inl error figure b-4: inl accuracy. b.12 differential nonlinearity (dnl) the differential nonlinearity (dnl) error (see figure b-5 ) is the measure of step size between codes in actual transfer function. the ideal step size between codes is 1 lsb. a dnl error of zero would imply that every code is exactly 1 lsb wide. if the dnl error is less than 1 lsb, the dac guarantees monotonic output and no missing codes. equation b-7 shows how to calculate the dnl error between any two adjacent codes in lsb. equation b-7: dnl error figure b-5: dnl accuracy. where: e inl is expressed in lsb. v calc_ideal = code * v lsb(measured) + v os v out(code = n) = the measured dac output voltage with a given dac register code v lsb(measured) = for measured: (v out(4000) - v out(100) )/3900 v os = measured offset voltage. e inl = ( v out - v calc_ideal ) v lsb(measured) 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 110 ideal transfer function actual transfer function inl = < -1 lsb inl = 0.5 lsb inl = - 1 lsb where: e dnl is expressed in lsb. v out(code = n) = the measured dac output voltage with a given dac register code. v lsb(measured) = for measured: (v out(4000) - v out(100) )/3900 e dnl = - 1 ( v out(code = n+1) - v out(code = n) ) v lsb(measured) 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 60 7 dnl = 2 lsb dnl = 0.5 lsb 110 ideal transfer function actual transfer function downloaded from: http:/// mcp48fvbxx ds20005466a-page 80 ? 2015 microchip technology inc. b.13 settling time settling time is the time delay required for the v out voltage to settle into its new output value. this time is measured from the start of code transition to when the v out voltage is within the specified accuracy. in the mcp48fvbxx, the settling time is a measure of the time delay until the v out voltage reaches within 0.5 lsb of its final value, when the volatile dac register changes from 1/4 to 3/4 of the full-scale range (12-bit device: 400h to c00h). b.14 major-code transition glitch major-code transition glitch is the impulse energy injected into the dac analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital code is changed by 1 lsb at the major carry transition. b.15 digital feedthrough digital feedthrough is the glitch that appears at the analog output, caused by coupling from the digital input pins of the device. the area of the glitch is expressed in nv-sec, and is measured with a full-scale change on the digital input pins. example: all 0 s to all 1 s and vice versa. the digital feedthrough is measured when the dac is not being written to the output register. b.16 -3 db bandwidth this is the frequency of the signal at the v ref pin that causes the voltage at the v out pin to fall -3 db value from a static value on the v ref pin. the output decreases due to the rc characteristics of the resistor ladder and the characteristics of the output buffer. b.17 power-supply sensitivity (pss) pss indicates how the output of the dac is affected by changes in the supply voltage. pss is the ratio of the change in v out to a change in v dd for mid-scale output of the dac. the v out is measured while the v dd is varied from 5.5v to 2.7v as a step (v ref voltage held constant), and expressed in %/%, which is the % change of the dac output voltage with respect to the % change of the v dd voltage. equation b-8: pss calculation b.18 power-supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. the v out is measured while the v dd is varied 10% (v ref voltage held constant), and expressed in db or v/v. b.19 v out temperature coefficient the v out temperature coefficient quantifies the error in the resistor ladders resistance ratio (dac register code value) and output buffer due to temperature drift. b.20 absolute temperature coefficient the absolute temperature coefficient quantifies the error in the end-to-end output voltage (nominal output voltage v out ) due to temperature drift. for a dac this error is typically not an issue due to the ratiometric aspect of the output. b.21 noise spectral density noise spectral density is a measurement of the devices internally-generated random noise, and is characterized as a spectral density (voltage per hz). it is measured by loading the dac to the mid-scale value and measuring the noise at the v out pin. it is measured in nv/ hz. example: 011...111 to 100...000 or 100...000 to 011...111 where: pss is expressed in %/%. v out(@5.5v) = the measured dac output voltage with v dd = 5.5v. v out(@2.7v) = the measured dac output voltage with v dd = 2.7v. pss v out @5.5v ?? v out @2.7v ?? ? v out @5.5v ?? ---------------------------------------------------------------------------------- - 5.5v 2.7v ? ?? 5.5v --------------------------------- ---------------------------------------------------------------------------------- - = downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 81 mcp48fvbxx product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: MCP48FVB01: single-channel 8-bit volatile dac with external + internal references mcp48fvb02: dual-channel 8-bit volatile dac with external + internal references mcp48fvb11: single-channel 10-bit volatile dac with external + internal references mcp48fvb12: dual-channel 10-bit volatile dac with external + internal references mcp48fvb21: single-channel 12-bit volatile dac with external + internal references mcp48fvb22: dual-channel 12-bit volatile dac with external + internal references tape and reel: t = tape and reel ( 1 ) blank = tube temperature range: e = -40c to +125c (extended) package: un = plastic micro small outline (msop), 10-lead examples: a) MCP48FVB01-e/un: 8-bit v out resolution, single channel, tube, extended temperature, 10-lead msop package b) MCP48FVB01t-e/un: 8-bit v out resolution, single channel, tape and reel, extended temperature, 10-lead msop package a) mcp48fvb11-e/un: 10-bit v out resolution, single channel, tube, extended temperature, 10-lead msop package b) mcp48fvb11t-e/un: 10-bit v out resolution, single channel, tape and reel, extended temperature, 10-lead msop package a) mcp48fvb21-e/un: 12-bit v out resolution, single channel, tube, extended temperature, 10-lead msop package b) mcp48fvb21t-e/un: 12-bit v out resolution, single channel, tape and reel, extended temperature, 10-lead msop package a) mcp48fvb22-e/un: 12-bit v out resolution, dual channel, tube, extended temperature, 10-lead msop package b) mcp48fvb22t-e/un: 12-bit v out resolution, dual channel, tape and reel, extended temperature, 10-lead msop package part no. x temperature range device /xx package x ( 1 ) tape and reel note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability for the tape and reel option. downloaded from: http:/// mcp48fvbxx ds20005466a-page 82 ? 2015 microchip technology inc. notes: downloaded from: http:/// ? 2015 microchip technology inc. ds20005466a-page 83 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0047-9 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ds20005466a-page 84 ? 2015 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 07/14/15 downloaded from: http:/// |
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